Datasheet > ADP3110KRZ1

ADP3110KRZ1

更新时间： 2022-04-23 23:00:11

品牌	Logo	应用领域
亚德诺 - ADI		驱动器
页数	文件大小	规格书
12页	242K
描述
Dual Bootstrapped, 12 V MOSFET Driver with Output Disable

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ADP3110KRZ1 数据手册

ADP3110

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

BST

DRVH

ADP3110

PGND

DRVL

TOP VIEW

(Not to Scale)

VCC

Figure 2. 8-Lead SOIC_N Pin Configuration

Table 3. Pin Function Descriptions

Pin No. Mnemonic Description

BST

Upper MOSFET Floating Bootstrap Supply. A capacitor connected between the BST and SW pins holds this

bootstrapped voltage for the high-side MOSFET as it is switched.

Logic Level PWM Input. This pin has primary control of the driver outputs. In normal operation, pulling this pin

low turns on the low-side driver; pulling it high turns on the high-side driver.

Output Disable. When low, this pin disables normal operation, forcing DRVH and DRVL low.

Input Supply. This pin should be bypassed to PGND with ~1 μF ceramic capacitor.

Synchronous Rectifier Drive. Output drive for the lower (synchronous rectifier) MOSFET.

Power Ground. This pin should be closely connected to the source of the lower MOSFET.

Switch Node Connection. This pin is connected to the buck-switching node, close to the upper MOSFET’s

source. It is the floating return for the upper MOSFET drive signal. It is also used to monitor the switched voltage

to prevent turn-on of the lower MOSFET until the voltage is below ~1 V.

VCC

DRVL

PGND

DRVH

Buck Drive. Output drive for the upper (buck) MOSFET.

Rev. 0 | Page 5 of 12

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