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ADP3110KRZ1 PDF预览

ADP3110KRZ1

更新时间: 2022-04-23 23:00:11
品牌 Logo 应用领域
亚德诺 - ADI 驱动器
页数 文件大小 规格书
12页 242K
描述
Dual Bootstrapped, 12 V MOSFET Driver with Output Disable

ADP3110KRZ1 数据手册

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ADP3110  
SPECIFICATIONS  
VCC = 12 V, BST = 4 V to 26 V, TA = 25°C, unless otherwise noted.  
Table 1.1  
Parameter  
Symbol  
Conditions  
Min  
Typ  
Max  
Unit  
PWM INPUT  
Input Voltage High2  
Input Voltage Low2  
Input Current2  
Hysteresis2  
2.0  
V
V
μA  
mV  
0.8  
+1  
−1  
90  
250  
OD INPUT  
Input Voltage High2  
Input Voltage Low2  
Input Current 2  
Hysteresis2  
2.0  
V
V
μA  
mV  
ns  
0.8  
+1  
−1  
90  
250  
20  
Propagation Delay Times3  
tpdlOD  
See Figure 3  
See Figure 3  
35  
55  
40  
ns  
tpdhOD  
HIGH-SIDE DRIVER  
Output Resistance, Sourcing Current  
Output Resistance, Sinking Current  
Output Resistance, Unbiased  
Transition Times  
BST to SW = 12 V  
BST to SW = 12 V  
BST to SW = 0 V  
BST to SW = 12 V, CLOAD = 3 nF, see Figure 4  
BST to SW = 12 V, CLOAD = 3 nF, see Figure 4  
BST to SW = 12 V, CLOAD = 3 nF,see Figure 4  
BST to SW = 12 V, CLOAD = 3 nF, see Figure 4  
SW to PGND  
3.8  
1.4  
10  
40  
30  
45  
25  
10  
4.4  
1.8  
Ω
Ω
RDRV + SW  
kΩ  
ns  
ns  
ns  
ns  
kΩ  
trDRVH  
tfDRVH  
tpdhDRVH  
tpdlDRVH  
RSW − PGND  
55  
45  
65  
35  
Propagation Delay Times3  
SW Pull Down Resistance  
LOW-SIDE DRIVER  
Output Resistance, Sourcing Current  
Output Resistance, Sinking Current  
Output Resistance, Unbiased  
Transition Times  
3.4  
1.4  
10  
40  
20  
15  
30  
190  
150  
4.0  
1.8  
Ω
Ω
RDRVL − PGND  
VCC = PGND  
kΩ  
ns  
ns  
ns  
ns  
ns  
ns  
trDRVL  
tfDRVL  
tpdhDRVL  
tpdlDRVL  
CLOAD = 3 nF, see Figure 4  
CLOAD = 3 nF, see Figure 4  
CLOAD = 3 nF, see Figure 4  
CLOAD = 3 nF, see Figure 4  
SW = 5 V  
50  
30  
35  
40  
Propagation Delay Times3  
Time-out Delay  
110  
95  
SW = PGND  
SUPPLY  
Supply Voltage Range2  
Supply Current2  
UVLO Voltage2  
Hysteresis2  
VCC  
ISYS  
4.15  
1.5  
13.2  
5
3.0  
V
mA  
V
BST = 12 V, IN = 0 V  
VCC rising  
2
350  
mV  
1 All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC) methods.  
2 Specifications apply over the full operating temperature range TA = 0°C to 85°C.  
3 For propagation delays, tpdh refers to the specified signal going high, and tpdl refers to it going low.  
Rev. 0 | Page 3 of 12  
 
 
 

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