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ADP1740ACPZ-1.8-R7 PDF预览

ADP1740ACPZ-1.8-R7

更新时间： 2024-02-12 18:42:18
品牌 Logo 应用领域
亚德诺 - ADI 稳压器调节器输出元件
页数 文件大小 规格书
20页 743K
描述
2 A, Low VIN, Low Dropout Linear Regulator

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ADP1740ACPZ-1.8-R7 技术参数

是否无铅： 含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：QFN
包装说明：HVQCCN, LCC16,.16SQ,25针数：16
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：1.18
可调性：FIXED最大回动电压 1：0.28 V
标称回动电压 1：0.16 V最大绝对输入电压：3.6 V
最大输入电压：3.6 V最小输入电压：1.6 V
JESD-30 代码：S-XQCC-N16JESD-609代码：e3
长度：4 mm最大电网调整率：0.00756%
最大负载调整率：0.0179%湿度敏感等级：3
功能数量：1输出次数：1
端子数量：16工作温度TJ-Max：125 °C
工作温度TJ-Min：-40 °C最大输出电流 1：2 A
最大输出电压 1：1.836 V最小输出电压 1：1.764 V
标称输出电压 1：1.8 V封装主体材料：UNSPECIFIED
封装代码：HVQCCN封装等效代码：LCC16,.16SQ,25
封装形状：SQUARE封装形式：CHIP CARRIER
包装方法：TAPE AND REEL峰值回流温度（摄氏度）：260
认证状态：Not Qualified调节器类型：FIXED POSITIVE SINGLE OUTPUT LDO REGULATOR
座面最大高度：1 mm子类别：Other Regulators
表面贴装：YES技术：CMOS
端子面层：Matte Tin (Sn)端子形式：NO LEAD
端子节距：0.65 mm端子位置：QUAD
处于峰值回流温度下的最长时间：40最大电压容差：2%
宽度：4 mmBase Number Matches：1

ADP1740ACPZ-1.8-R7 数据手册

 浏览型号ADP1740ACPZ-1.8-R7的Datasheet PDF文件第11页浏览型号ADP1740ACPZ-1.8-R7的Datasheet PDF文件第12页浏览型号ADP1740ACPZ-1.8-R7的Datasheet PDF文件第13页浏览型号ADP1740ACPZ-1.8-R7的Datasheet PDF文件第15页浏览型号ADP1740ACPZ-1.8-R7的Datasheet PDF文件第16页浏览型号ADP1740ACPZ-1.8-R7的Datasheet PDF文件第17页 
ADP1740/ADP1741  
Data Sheet  
APPLICATIONS INFORMATION  
CAPACITOR SELECTION  
Input Bypass Capacitor  
Connecting a 4.7 µF capacitor from the VIN pin to GND  
reduces the circuit sensitivity to printed circuit board (PCB)  
layout, especially when long input traces or high source  
impedance are encountered. If output capacitance greater than  
4.7 µF is required, it is recommended that the input capacitor be  
increased to match it.  
Output Capacitor  
The ADP1740/ADP1741 are designed for operation with small,  
space-saving ceramic capacitors, but they function with most  
commonly used capacitors as long as care is taken with regard  
to the effective series resistance (ESR) value. The ESR of the  
output capacitor affects the stability of the LDO control loop. A  
minimum of 3.3 µF capacitance with an ESR of 100 mΩ or less is  
recommended to ensure the stability of the ADP1740/ADP1741.  
Transient response to changes in load current is also affected by  
output capacitance. Using a larger value of output capacitance  
improves the transient response of the ADP1740/ADP1741 to  
large changes in load current. Figure 33 and Figure 34 show the  
transient responses for output capacitance values of 4.7 µF and  
22 µF, respectively.  
Input and Output Capacitor Properties  
Any good quality ceramic capacitors can be used with the  
ADP1740/ADP1741, as long as they meet the minimum  
capacitance and maximum ESR requirements. Ceramic  
capacitors are manufactured with a variety of dielectrics, each  
with different behavior over temperature and applied voltage.  
Capacitors must have a dielectric adequate to ensure the  
minimum capacitance over the necessary temperature range  
and dc bias conditions. X5R or X7R dielectrics with a voltage  
rating of 6.3 V or 10 V are recommended. Y5V and Z5U  
dielectrics are not recommended, due to their poor temperature  
and dc bias characteristics.  
I
T
LOAD  
1A/DIV  
1mA TO 2A LOAD STEP, 2.5A/µs  
1
2
Figure 35 shows the capacitance vs. voltage bias characteristics  
of an 0805 case, 4.7 μF, 10 V, X5R capacitor. The voltage stability  
of a capacitor is strongly influenced by the capacitor size and  
voltage rating. In general, a capacitor in a larger package or with  
a higher voltage rating exhibits better stability. The temperature  
variation of the X5R dielectric is approximately 15% over the  
−40°C to +85°C temperature range and is not a function of  
package size or voltage rating.  
V
OUT  
50mV/DIV  
V
C
= 3.6V, V  
= C  
OUT  
= 1.5V  
= 4.7µF  
IN  
OUT  
IN  
B
B
W
CH1 1.0A  
Ω
CH2 50.0mV  
M1.0µs  
A CH1  
380mA  
W
5
T
10.80%  
MURATA P/N GRM219R61A475KE34  
Figure 33. Output Transient Response, COUT = 4.7 µF  
4
3
2
1
0
I
T
LOAD  
1A/DIV  
1mA TO 2A LOAD STEP, 2.5A/µs  
1
2
V
OUT  
50mV/DIV  
0
2
4
6
8
10  
VOLTAGE BIAS (V)  
V
C
= 3.6V, V  
= C  
OUT  
= 1.5V  
= 22µF  
Figure 35. Capacitance vs. Voltage Bias Characteristics  
IN  
OUT  
IN  
Use Equation 3 to determine the worst-case capacitance,  
accounting for capacitor variation over temperature, com-  
ponent tolerance, and voltage.  
B
B
W
CH1 1.0A  
Ω
CH2 50.0mV  
M1.0µs  
A CH1  
880mA  
W
T
11.80%  
Figure 34. Output Transient Response, COUT = 22 µF  
C
EFF = COUT × (1 − TEMPCO) × (1 − TOL)  
where:  
EFF is the effective capacitance at the operating voltage.  
(3)  
C
TEMPCO is the worst-case capacitor temperature coefficient.  
TOL is the worst-case component tolerance.  
Rev. E | Page 14 of 20  
 
 
 
 
 
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