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ADP150ACBZ-3.0-R7 PDF预览

ADP150ACBZ-3.0-R7

更新时间： 2024-02-06 11:22:50
品牌 Logo 应用领域
亚德诺 - ADI 线性稳压器IC调节器电源电路输出元件PC
页数 文件大小 规格书
20页 556K
描述
Ultralow Noise, 150 mA CMOS Linear Regulator

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ADP150ACBZ-3.0-R7 技术参数

是否无铅： 含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：BGA
包装说明：0.80 X 0.80 MM, 0.40 MM PITCH, ROHS COMPLIANT, WLCSP-4针数：4
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：1.62
Samacsys Confidence：Samacsys Status：Released
Samacsys PartID：421102Samacsys Pin Count：4
Samacsys Part Category：Integrated CircuitSamacsys Package Category：Other
Samacsys Footprint Name：BGA4C40P2X2_76X76X66Samacsys Released Date：2017-01-11 11:21:59
Is Samacsys：N可调性：FIXED
最大回动电压 1：0.16 V标称回动电压 1：0.105 V
最大绝对输入电压：6.5 V最大输入电压：5.5 V
最小输入电压：2.2 VJESD-30 代码：S-PBGA-B4
JESD-609代码：e1长度：0.76 mm
最大电网调整率：0.00315%最大负载调整率：0.027%
湿度敏感等级：1功能数量：1
输出次数：1端子数量：4
工作温度TJ-Max：125 °C工作温度TJ-Min：-40 °C
最大输出电流 1：0.15 A最大输出电压 1：3.045 V
最小输出电压 1：2.94 V标称输出电压 1：3 V
封装主体材料：PLASTIC/EPOXY封装代码：VFBGA
封装等效代码：BGA4,2X2,16封装形状：SQUARE
封装形式：GRID ARRAY, VERY THIN PROFILE, FINE PITCH包装方法：TAPE AND REEL
峰值回流温度（摄氏度）：260认证状态：Not Qualified
调节器类型：FIXED POSITIVE SINGLE OUTPUT LDO REGULATOR座面最大高度：0.66 mm
子类别：Other Regulators表面贴装：YES
技术：CMOS端子面层：Tin/Silver/Copper (Sn/Ag/Cu)
端子形式：BALL端子节距：0.4 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：30
宽度：0.76 mmBase Number Matches：1

ADP150ACBZ-3.0-R7 数据手册

 浏览型号ADP150ACBZ-3.0-R7的Datasheet PDF文件第9页浏览型号ADP150ACBZ-3.0-R7的Datasheet PDF文件第10页浏览型号ADP150ACBZ-3.0-R7的Datasheet PDF文件第11页浏览型号ADP150ACBZ-3.0-R7的Datasheet PDF文件第13页浏览型号ADP150ACBZ-3.0-R7的Datasheet PDF文件第14页浏览型号ADP150ACBZ-3.0-R7的Datasheet PDF文件第15页 
ADP150  
APPLICATIONS INFORMATION  
CAPACITOR SELECTION  
Input and Output Capacitor Properties  
Any good quality ceramic capacitors can be used with the ADP150,  
as long as they meet the minimum capacitance and maximum  
ESR requirements. Ceramic capacitors are manufactured with a  
variety of dielectrics, each with different behavior over temperature  
and applied voltage. Capacitors must have a dielectric adequate to  
ensure the minimum capacitance over the necessary temperature  
range and dc bias conditions. X5R or X7R dielectrics with a  
voltage rating of 6.3 V or 10 V are recommended. Y5V and Z5U  
dielectrics are not recommended, due to their poor temperature  
and dc bias characteristics.  
Output Capacitor  
The ADP150 is designed for operation with small, space-saving  
ceramic capacitors but functions with most commonly used  
capacitors as long as care is taken with regard to the effective  
series resistance (ESR) value. The ESR of the output capacitor  
affects the stability of the LDO control loop. A minimum of 1 µF  
capacitance with an ESR of 1 Ω or less is recommended to  
ensure the stability of the ADP150. The transient response to  
changes in load current is also affected by output capacitance.  
Using a larger value of output capacitance improves the transient  
response of the ADP150 to large changes in the load current.  
Figure 27 and Figure 28 show the transient responses for output  
capacitance values of 1 µF and 4.7 µF, respectively.  
Figure 29 depicts the capacitance vs. the voltage bias characteristic  
of a 0402, 1 µF, 10 V, X5R capacitor. The voltage stability of a  
capacitor is strongly influenced by the capacitor size and voltage  
rating. In general, a capacitor in a larger package or higher voltage  
rating exhibits better stability. The temperature variation of the X5R  
dielectric is about 15% over the −40°C to +85°C temperature  
range and is not a function of package or voltage rating.  
1.2  
T
I
OUT  
1mA TO 150mA LOAD STEP  
1
1.0  
0.8  
0.6  
0.4  
0.2  
0
2
V
OUT  
V
V
= 3.7V  
= 3.3V  
IN  
OUT  
CH1 100mA CH2 50mV  
M1.0µs  
T
A CH1  
100mA  
716.000µs  
Figure 27. Output Transient Response, COUT = 1 µF  
T
0
2
4
6
8
10  
BIAS VOLTAGE (V)  
I
OUT  
1mA TO 150mA LOAD STEP  
Figure 29. Capacitance vs. Voltage Bias Characteristic  
1
2
Use Equation 1 to determine the worst-case capacitance,  
accounting for capacitor variation over temperature, component  
tolerance, and voltage.  
CEFF = CBIAS × (1 − TEMPCO) × (1 − TOL)  
(1)  
V
OUT  
where:  
C
BIAS is the effective capacitance at the operating voltage.  
V
V
= 3.7V  
= 3.3V  
IN  
OUT  
TEMPCO is the worst-case capacitor temperature coefficient.  
TOL is the worst-case component tolerance.  
CH1 100mA CH2 50mV  
M1.0µs  
A CH1  
108mA  
T
240.000ns  
In this example, the worst-case temperature coefficient (TEMPCO)  
over −40°C to +85°C is assumed to be 15% for an X5R dielectric.  
The tolerance of the capacitor (TOL) is assumed to be 10%, and  
the CBIAS is 0.94 µF at 1.8 V, as shown in Figure 29.  
Figure 28. Output Transient Response, COUT = 4.7 µF  
Input Bypass Capacitor  
Connecting a 1 µF capacitor from VIN to GND reduces the  
circuit sensitivity to the PCB layout, especially when long input  
traces or high source impedance is encountered. If greater than  
1 µF of output capacitance is required, increase the input capacitor  
to match the output capacitor.  
Substituting these values in Equation 1 yields  
CEFF = 0.94 µF × (1 − 0.15) × (1 − 0.1) = 0.719 µF  
Therefore, the capacitor chosen in this example meets the  
minimum capacitance requirement of the LDO over temperature  
and tolerance at the chosen output voltage.  
Rev. A | Page 12 of 20  
 
 
 
 
 
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