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ADP1173AN-3.3 PDF预览

ADP1173AN-3.3

更新时间： 2024-01-07 22:16:46
品牌 Logo 应用领域
其他 - ETC 开关光电二极管控制器
页数 文件大小 规格书
16页 432K
描述
Voltage-Mode SMPS Controller

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ADP1173AN-3.3 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Active零件包装代码：DIP
包装说明：DIP,针数：8
Reach Compliance Code：unknown风险等级：5.68
模拟集成电路 - 其他类型：SWITCHING REGULATOR控制模式：VOLTAGE-MODE
控制技术：PULSE FREQUENCY MODULATION最大输入电压：30 V
最小输入电压：2 V标称输入电压：3 V
JESD-30 代码：R-PDIP-T8JESD-609代码：e0
长度：9.88 mm湿度敏感等级：NOT SPECIFIED
功能数量：1端子数量：8
最高工作温度：70 °C最低工作温度：
最大输出电流：1.5 A封装主体材料：PLASTIC/EPOXY
封装代码：DIP封装形状：RECTANGULAR
封装形式：IN-LINE峰值回流温度（摄氏度）：NOT SPECIFIED
座面最大高度：5.33 mm表面贴装：NO
切换器配置：BOOST最大切换频率：32 kHz
温度等级：COMMERCIAL端子面层：TIN LEAD
端子形式：THROUGH-HOLE端子节距：2.54 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：7.62 mmBase Number Matches：1

ADP1173AN-3.3 数据手册

 浏览型号ADP1173AN-3.3的Datasheet PDF文件第8页浏览型号ADP1173AN-3.3的Datasheet PDF文件第9页浏览型号ADP1173AN-3.3的Datasheet PDF文件第10页浏览型号ADP1173AN-3.3的Datasheet PDF文件第12页浏览型号ADP1173AN-3.3的Datasheet PDF文件第13页浏览型号ADP1173AN-3.3的Datasheet PDF文件第14页 
ADP1173  
+5V  
The internal structure of the ILIM circuit is shown in Figure 21.  
Q1 is the ADP1173’s internal power switch, which is paralleled  
by sense transistor Q2. The relative sizes of Q1 and Q2 are  
scaled so that IQ2 is 0.5% of IQ1. Current flows to Q2 through an  
internal 80 Ω resistor and through the RLIM resistor. These two  
resistors parallel the base-emitter junction of the oscillator-  
disable transistor, Q3. When the voltage across R1 and RLIM  
exceeds 0.6 V, Q3 turns on and terminates the output pulse. If  
only the 80 Ω internal resistor is used (i.e., the ILIM pin is con-  
nected directly to VIN), the maximum switch current will be  
1.5 A. Figures 4 and 5 gives RLIM values for lower current-limit  
values.  
2
ADP1173  
1.245V  
100kΩ  
V
IN  
R1  
R2  
AO  
TO  
PROCESSOR  
REF  
6
V
SET  
BAT  
7
GND  
5
V
–1.245V  
LB  
12.5µA  
= BATTERY TRIP POINT  
R1 =  
V
LB  
R2 = 100kΩ  
Figure 22. Setting the Low Battery Detector Trip Point  
Figure 22 shows the gain block configured as a low battery  
monitor. Resistors R1 and R2 should be set to high values to  
reduce quiescent current, but not so high that bias current in the  
SET input causes large errors. A value of 100 kΩ for R2 is a  
good compromise. The value for R1 is then calculated from the  
formula:  
I
LIM  
R
LIM  
(EXTERNAL)  
V
IN  
80Ω  
(INTERNAL)  
R1  
SW1  
Q1  
Q3  
VLOBATT − 1.245V  
R1=  
DRIVER  
1.245V  
Q2  
OSCILLATOR  
R2  
SW2  
where VLOBATT is the desired low battery trip point. Since the  
gain block output is an open-collector NPN, a pull-up resistor  
should be connected to the positive logic power supply.  
Figure 21. Current Limit Operation  
The delay through the current limiting circuit is approximately  
2 µs. If the switch ON time is reduced to less than 4 µs, accu-  
racy of the current trip-point is reduced. Attempting to program  
a switch ON time of 2 µs or less will produce spurious responses  
in the switch ON time. However, the ADP1173 will still provide  
a properly regulated output voltage.  
5V  
2
ADP1173  
1.245mV  
47kΩ  
V
IN  
R1  
R2  
AO  
TO  
PROCESSOR  
REF  
6
V
SET  
BAT  
7
GND  
5
PROGRAMMING THE GAIN BLOCK  
R3  
The gain block of the ADP1173 can be used as a low-battery  
detector, error amplifier or linear post regulator. The gain block  
consists of an op amp with PNP inputs and an open-collector  
NPN output. The inverting input is internally connected to the  
ADP1173’s 1.245 V reference, while the noninverting input is  
available at the SET pin. The NPN output transistor will sink  
about 100 µA.  
1.6MΩ  
Figure 23. Adding Hysteresis to the Low Battery Detector  
REV. 0  
–11–  
1...891011121314...16

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