Programmable Low Voltage
1:10 LVDS Clock Driver
ADN4670
Data Sheet
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Low output skew <30 ps (typical)
CK
Distributes one differential clock input to 10 LVDS clock
outputs
Programmable—one of two differential clock inputs can be
selected (CLK0, CLK1) and individual differential clock
outputs enabled/disabled
SI
11-BIT SHIFT REGISTER
EN
11-BIT CONTROL REGISTER
12-BIT
COUNTER
10
9876543210
MUX
1
Signaling rate up to 1.1 GHz (typical)
Q9
Q9
2.375 V to 2.625 V power supply range
100 mV differential input threshold
Input common-mode range from rail-to-rail
I/O pins fail-safe during power-down: VDD = 0 V
Available in 32-lead LFCSP and LQFP packages
Industrial operating temperature range: −40°C to +85°C
0
Q8
Q8
CLK0
CLK0
0
1
Q7
Q7
CLK1
CLK1
MUX
Q6
Q6
APPLICATIONS
Q5
Q5
Clock distribution networks
Q4
Q4
Q3
Q3
Q2
Q2
Q1
Q1
Q0
Q0
Figure 1.
GENERAL DESCRIPTION
The ADN4670 is a low voltage differential signaling (LVDS)
clock driver that expands a differential clock input signal to
10 differential clock outputs. The device is programmable
using a simple serial interface, so that one of two clock inputs
first 10 bits determine which outputs are enabled (0 = disabled,
1 = enabled), while the 11th bit selects the clock input (0 =
CLK0, 1 = CLK1). A 12th clock pulse transfers data from the
shift register to the control register.
CLK0
CLK1
can be selected (CLK0/
or CLK1/
) and any of the
The ADN4670 is fully specified over the industrial temperature
range and is available in a 32-lead LFCSP and LQFP packages.
Q0
Q9
differential outputs (Q0/ to Q9/ ) can be enabled or
disabled (tristated). The ADN4670 is designed for use in 50 Ω
transmission line environments.
When the enable input EN is high, the device may be pro-
grammed by clocking 11 data bits into the shift register. The
Rev. A
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