Datasheet > ADMC401

ADMC401

更新时间： 2024-01-18 04:39:31

品牌	Logo	应用领域
亚德诺 - ADI		电机控制器
页数	文件大小	规格书
60页	413K
描述
Single-Chip, DSP-Based High Performance Motor Controller

阅读下载

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

ADMC401 技术参数

是否无铅：	含铅	是否Rohs认证：	符合
生命周期：	Active	包装说明：	QFP, QFP144,.87SQ,20
针数：	144	Reach Compliance Code：	compliant
风险等级：	8.4	JESD-30 代码：	S-PQFP-G144
JESD-609代码：	e3	湿度敏感等级：	3
端子数量：	144	最高工作温度：	85 °C
最低工作温度：	-40 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	QFP	封装等效代码：	QFP144,.87SQ,20
封装形状：	SQUARE	封装形式：	FLATPACK
电源：	5 V	认证状态：	Not Qualified
子类别：	Motion Control Electronics	标称供电电压 (Vsup)：	5 V
表面贴装：	YES	技术：	CMOS
温度等级：	INDUSTRIAL	端子面层：	Matte Tin (Sn)
端子形式：	GULL WING	端子节距：	0.5 mm
端子位置：	QUAD	Base Number Matches：	1

ADMC401 数据手册

ADMC401

MEMWAIT (R/W)

DM (0x3FFE)

DWAIT4

DWAIT3

DWAIT2

DWAIT1

DWAIT0

ROM ENABLE

1 = ENABLE

0 = DISABLE

NOTE: IN STANDALONE MODE (MMAP = BMODE = 1)

THE ROM MONITOR WRITES 0x8000 TO THIS REGISTER.

SPORT0_RX_WORDS1 (R/W)

SPORT0_TX_WORDS1 (R/W)

1 = CHANNEL ENABLE

0 = CHANNEL IGNORED

1 = CHANNEL ENABLE

0 = CHANNEL IGNORED

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

DM (0x3FFA)

DM (0x3FF9)

DM (0x3FF8)

DM (0x3FF7)

SPORT0_RX_WORDS0 (R/W)

15 14 13 12 11 10

SPORT0_TX_WORDS0 (R/W)

15 14 13 12 11 10

SPORT0_CTRL_REG (R/W)

DM (0x3FF6)

MULTICHANNEL ENABLE MCE

SLEN SERIAL WORD LENGTH

IINTERNAL SERIAL CLOCK GENERATION ISCLK

DTYPE DATA FORMAT

00 = RIGHT JUSTIFY, ZERO-FILLED UNUSED MSBS

01 = RIGHT JUSTIFY, SIGN EXTEND INTO UNUSED MSBS

10 = COMPAND USING ꢁ-LAW

RECEIVE FRAME SYNC REQUIRED RFSR

RECEIVE FRAME SYNC WIDTH RFSW

11 = COMPAND USING A-LAW

MULTI CHANNEL FRAME DELAY MFD

ONLY IF MULTICHANNEL MODE ENABLED)

INVRFS IINVERT RECEIVE FRAME SYNC

INVTFS INVERT TRANSMIT FRAME SYNC

(OR INVTDV INVERT TRANSMIT DATA VALID

ONLY IF MULTICHANNEL MODE ENABLED)

TRANSMIT FRAME SYNC REQUIRED TFSR

TRANSMIT FRAME SYNC WIDTH TFSW

IRFS INTERNAL RECEIVE FRAME SYNC ENABLE

ITFS INTERNAL TRANSMIT FRAME SYNC ENABLE

(OR MCL MULTICHANNEL LENGTH; 1 = 32 WORDS, 0 = 24 WORDS

ONLY IF MULTICHANNEL MODE ENABLED)

Figure 45. Structure of Registers of ADMC401

Default bit values are shown; if no value is shown, the bit field is undefined at reset. Reserved bits are shown on a gray field—these

bits should always be written as shown.

–57–

REV. B

1...54 55 565758 59 60

下载PDF

与ADMC401相关器件

型号	品牌	描述	获取价格	数据表
ADMC401-ADVEVALKIT	ADI	Single-Chip, DSP-Based High Performance Motor Controller	获取价格
ADMC401BST	ADI	Single-Chip, DSP-Based High Performance Motor Controller	获取价格
ADMC401BSTZ	ADI	Single-Chip, DSP-Based High Performance Motor Controller	获取价格
ADMC401-PB	ADI	Single-Chip, DSP-Based High Performance Motor Controller	获取价格
ADMCF326	ADI	28-Lead Flash Memory DSP Motor Controller	获取价格
ADMCF326BN	ETC	Controller Miscellaneous - Datasheet Reference	获取价格