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ADMC331BST

更新时间： 2024-02-28 08:57:15
品牌 Logo 应用领域
亚德诺 - ADI 电机控制器
页数 文件大小 规格书
36页 247K
描述
Single Chip DSP Motor Controller

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ADMC331BST 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：QFP包装说明：PLASTIC, TQFP-80
针数：80Reach Compliance Code：not_compliant
ECCN代码：EAR99HTS代码：8542.31.00.01
风险等级：5.89地址总线宽度：
桶式移位器：YES边界扫描：NO
最大时钟频率：16.384 MHz外部数据总线宽度：
格式：FIXED POINT内部总线架构：MULTIPLE
JESD-30 代码：S-PQFP-G80JESD-609代码：e0
长度：14 mm低功率模式：YES
端子数量：80最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：LQFP封装形状：SQUARE
封装形式：FLATPACK, LOW PROFILE峰值回流温度（摄氏度）：220
认证状态：Not Qualified座面最大高度：1.6 mm
最大供电电压：5.5 V最小供电电压：4.5 V
标称供电电压：5 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：TIN LEAD端子形式：GULL WING
端子节距：0.65 mm端子位置：QUAD
处于峰值回流温度下的最长时间：30宽度：14 mm
uPs/uCs/外围集成电路类型：DIGITAL SIGNAL PROCESSOR, OTHERBase Number Matches：1

ADMC331BST 数据手册

 浏览型号ADMC331BST的Datasheet PDF文件第7页浏览型号ADMC331BST的Datasheet PDF文件第8页浏览型号ADMC331BST的Datasheet PDF文件第9页浏览型号ADMC331BST的Datasheet PDF文件第11页浏览型号ADMC331BST的Datasheet PDF文件第12页浏览型号ADMC331BST的Datasheet PDF文件第13页 
ADMC331  
PIN FUNCTION DESCRIPTION  
Memory Map  
The ADMC331 is available in an 80-lead TQFP package. Table I  
contains the pin descriptions.  
The ADMC331 has two distinct memory types: program  
memory and data memory. In general, program memory contains  
user code and coefficients, while the data memory is used to store  
variables and data during program execution. Both program  
memory RAM and ROM are provided on the ADMC331. Pro-  
gram memory RAM is arranged as one contiguous 2K × 24-bit  
block, starting at address 0x0000. Program memory ROM is  
located at address 0x0800. Data memory is arranged as a 1K ×  
16-bit block starting at address 0x3800. The motor control  
peripherals are memory mapped into a region of the data  
memory space starting at 0x2000. The complete program and  
data memory maps are given in Tables II and III, respectively.  
Table I. Pin List  
Pin  
#
Group  
Name  
of  
Input/  
Pins Output Function  
RESET  
1
5
I/P  
Processor Reset Input.  
SPORT0  
I/P, O/P Serial Port 0 Pins (TFS0, RFS0,  
DT0, DR0, SCLK0).  
SPORT1  
6
I/P, O/P Serial Port 1 Pins (TFS1, RFS1,  
DT1, DR1A, DR1B, SCLK1).  
Table II. Program Memory Map  
CLKOUT  
1
2
O/P  
Processor Clock Output.  
Memory  
Type  
CLKIN, XTAL  
I/P, O/P External Clock or Quartz Crystal  
Connection Point.  
Address Range  
Function  
0x0000–0x002F  
0x0030–0x071F  
0x0720–0x07EC  
0x07ED–0x07FF  
0x0800–0x0DEC  
0x0DED–0x0FEA  
RAM  
RAM  
RAM  
RAM  
ROM  
ROM  
Interrupt Vector Table  
User Program Space  
Reserved by Debugger  
Reserved by Monitor  
ROM Monitor  
ROM Math and Motor  
Control Utilities  
PIO0–PIO23  
AUX0–AUX1  
AH–CL  
24  
2
I/P, O/P Digital I/O Port Pins.  
O/P  
O/P  
I/P  
Auxiliary PWM Outputs.  
PWM Outputs.  
6
PWMTRIP  
PWMPOL  
PWMSYNC  
PWMSR  
1
PWM Trip Signal.  
1
I/P  
PWM Polarity Pin.  
1
O/P  
I/P  
PWM Synchronization Pin.  
Switch Reluctance Mode Pin.  
Analog Inputs.  
0x0FEB–0x0FFF  
ROM  
Reserved  
1
V1–V3,  
3
I/P  
Table III. Data Memory Map  
Memory  
VAUX0–VAUX3 4  
I/P  
Auxiliary Analog Input  
ADC Capacitor Input.  
ADC Constant Current Source.  
Voltage Reference Output.  
Analog Power Supply.  
Analog Ground.  
CAPIN  
ICONST  
VREF  
AVDD  
1
I/P  
Address Range  
Type  
Function  
1
O/P  
O/P  
0x0000–0x1FFF  
0x2000–0x20FF  
0x2100–0x37FF  
0x3800–0x3B5F  
0x3B60–0x3BFF  
0x3C00–0x3FFF  
Reserved  
Memory Mapped Registers  
Reserved  
User Data Space  
Reserved by Monitor  
Memory Mapped Registers  
1
1
AGND  
SGND  
VDD  
1
RAM  
RAM  
1
Analog Signal Ground  
Digital Power Supply.  
Digital Ground.  
5
GND  
11  
ROM Code  
The 2K × 24-bit block of program memory ROM starting at ad-  
dress 0x0800 contains a monitor function that is used to download  
and execute user programs via the serial port. In addition, the  
monitor function supports an interactive mode in which commands  
are received and processed from a host. An example of such a host  
is the Windows®-based Motion Control Debugger, which is part of  
the software development system for the ADMC331. In the inter-  
active mode, the host can access both the internal DSP and periph-  
eral motor control registers of the ADMC331, read and write to  
both program and data memory, implement breakpoints and per-  
form single-step and run/halt operation as part of the program  
debugging cycle.  
INTERRUPT OVERVIEW  
The ADMC331 can respond to 34 different interrupt sources  
with minimal overhead, 8 of which are internal DSP core  
interrupts and 26 interrupts from the motor control peripherals.  
The 8 DSP core interrupts are SPORT0 receive and transmit,  
SPORT1 receive (or IRQ0) and transmit (or IRQ1), the internal  
timer and two software interrupts. The motor control peripheral  
interrupts are the 24 peripheral I/Os and two from the PWM  
(PWMSYNC pulse and PWMTRIP). All motor control inter-  
rupts are multiplexed into the DSP core through the peripheral  
IRQ2 interrupt. The interrupts are internally prioritized and indi-  
vidually maskable. A detailed description of the entire inter-  
rupt system of the ADMC331 is given later, following a more  
detailed description of each peripheral block.  
In addition to the monitor function, the program memory ROM  
contains a number of useful mathematical and motor control util-  
ities that can be called as subroutines from the user code. A com-  
plete list of these ROM functions is given in Table IV. The start  
address of the function in the program memory ROM is also given.  
Refer to the ADMC331 DSP Motor Controller Developer’s Reference  
Manual for more details of the ROM functions.  
Windows is a registered trademark of Microsoft Corporation.  
–10–  
REV. B  
1...78910111213...36

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