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ADM8691ARW-REEL

更新时间： 2024-01-22 12:08:58
品牌 Logo 应用领域
亚德诺 - ADI 微处理器监控
页数 文件大小 规格书
16页 209K
描述
2-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO16, MS-013AA, SOIC-16

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ADM8691ARW-REEL 技术参数

是否无铅： 含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：SOIC
包装说明：SOP, SOP16,.4针数：16
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：1.3
其他特性：RESET THRESHOLD VOLTAGE IS 4.65V可调阈值：NO
模拟集成电路 - 其他类型：POWER SUPPLY MANAGEMENT CIRCUITJESD-30 代码：R-PDSO-G16
JESD-609代码：e3长度：10.3 mm
湿度敏感等级：1信道数量：2
功能数量：1端子数量：16
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装等效代码：SOP16,.4封装形状：RECTANGULAR
封装形式：SMALL OUTLINE峰值回流温度（摄氏度）：260
电源：5 V认证状态：Not Qualified
座面最大高度：2.65 mm子类别：Power Management Circuits
最大供电电流 (Isup)：0.2 mA最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.75 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Matte Tin (Sn)
端子形式：GULL WING端子节距：1.27 mm
端子位置：DUAL处于峰值回流温度下的最长时间：30
宽度：7.5 mmBase Number Matches：1

ADM8691ARW-REEL 数据手册

 浏览型号ADM8691ARW-REEL的Datasheet PDF文件第5页浏览型号ADM8691ARW-REEL的Datasheet PDF文件第6页浏览型号ADM8691ARW-REEL的Datasheet PDF文件第7页浏览型号ADM8691ARW-REEL的Datasheet PDF文件第9页浏览型号ADM8691ARW-REEL的Datasheet PDF文件第10页浏览型号ADM8691ARW-REEL的Datasheet PDF文件第11页 
ADM8690–ADM8695  
(PFI) is compared to an internal +1.3 V reference. T he Power  
Fail Output (PFO) goes low when the voltage at PFI is less than  
1.3 V. T ypically PFI is driven by an external voltage divider that  
senses either the unregulated dc input to the system’s 5 V regu-  
lator or the regulated 5 V output. T he voltage divider ratio can  
be chosen such that the voltage at PFI falls below 1.3 V several  
milliseconds before the +5 V power supply falls below the reset  
threshold. PFO is normally used to interrupt the microprocessor  
so that data can be stored in RAM and the shut down procedure  
executed before power is lost  
CE Gating and RAM Wr ite P r otection (AD M8691/AD M8693/  
AD M8695)  
T he ADM8691/ADM8693/ADM8695 products include  
memory protection circuitry which ensures the integrity of data  
in memory by preventing write operations when VCC is at an in-  
valid level. T here are two additional pins, CEIN and CEOUT  
,
which may be used to control the Chip Enable or Write inputs  
of CMOS RAM. When VCC is present, CEOUT is a buffered rep-  
lica of CEIN, with a 3 ns propagation delay. When VCC falls be-  
low the reset voltage threshold or VBAT T, an internal gate forces  
CEOUT high, independent of CEIN  
.
INPUT  
POWER  
ADM869x  
CEOUT typically drives the CE, CS or write input of battery  
backed up CMOS RAM. T his ensures the integrity of the data  
in memory by preventing write operations when VCC is at an in-  
valid level. Similar protection of EEPROMs can be achieved by  
using the CEOUT to drive the store or write inputs.  
R1  
R2  
1.3V  
POWER  
FAIL  
PFO  
OUTPUT  
POWER  
FAIL  
INPUT  
Figure 7. Power Fail Com parator  
Table II. Input and O utput Status In Battery Backup Mode  
ADM869x  
CE  
IN  
CE  
OUT  
Signal  
Status  
V
V
LOW = 0  
OK = 1  
CC  
CC  
VOUT  
VOUT is connected to VBAT T via an internal  
PMOS switch.  
Figure 5. Chip Enable Gating  
RESET  
Logic low.  
RESET  
Logic high. T he open circuit output voltage is  
V2  
V2  
equal to VOUT  
.
V
V1  
V1  
CC  
LOW LINE  
Logic low.  
BAT T ON  
Logic high. T he open circuit voltage is equal to  
VOUT.  
t1  
t1  
RESET  
WDI  
WDI is ignored. It is internally disconnected  
from the internal pull-up resistor and does not  
source or sink current as long as its input voltage  
is between GND and VOUT . T he input voltage  
does not affect supply current.  
LOW LINE  
WDO  
Logic high. T he open circuit voltage is equal  
to VOUT  
.
CE  
IN  
PFI  
T he Power Fail Comparator is turned off and  
has no effect on the Power Fail Output.  
PFO  
CEIN  
Logic low.  
CE  
OUT  
CEIN is ignored. It is internally disconnected  
from its internal pull-up and does not source or  
sink current as long as its input voltage is  
between GND and VOUT . T he input voltage  
does not affect supply current.  
t1 = RESET TIME  
V1 = RESET VOLTAGE THRESHOLD LOW  
V2 = RESET VOLTAGE THRESHOLD HIGH  
HYSTERESIS = V2–V1  
CEOUT  
Logic high. T he open circuit voltage is equal to  
Figure 6. Chip Enable Tim ing  
P ower Fail War ning Com par ator  
An additional comparator is provided for early warning of fail-  
ure in the microprocessor’s power supply. T he Power Fail Input  
VOUT  
.
OSC IN  
OSC IN is ignored.  
OSC SEL is ignored.  
OSC SEL  
–8–  
REV. 0  
1...567891011...16

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