Data Sheet
ADM7170
An external capacitor connected to the SS pin determines the
soft-start time. The SS pin can be left open for a typical 380 μs
start-up time. Do not ground this pin. When an external soft
start capacitor is used, the soft start time is determined by the
following equation:
C
NR is chosen by setting the reactance of CNR equal to RFB1
−
RNR at a frequency between 0.5 Hz and 10 Hz. This sets the
frequency where the ac gain of the error amplifier is 3 dB
less than its dc gain.
ADM7170
V
= 6.5V
V
= 6.0V
OUT
IN
SSTIME (sec) = tSTART-UP at 0 nF + (0.6 × CSS)/ISS
VIN
VIN
VOUT
VOUT
C
4.7µF
R
C
OUT
4.7µF
IN
FB1
C
1µF
NR
where:
R
NR
5kΩ
200kΩ
SENSE
tSTART-UP at 0 nF is the start-up time at CSS = 0 nF (typically 380 μs).
ON
R
50kΩ
FB2
C
SS is the soft start capacitor (F).
EN
SS
GND
C
SS
OFF
ISS is the soft start current (typically 1 μA).
1nF
3.5
Figure 62. Noise Reduction Modification
3.0
2.5
2.0
1.5
1.0
0.5
0
Assuming the noise of a fixed output LDO is approximately
5 μV, identify the noise of the adjustable LDO by using the
following formula:
Noise = 5 μV × (RPAR + RFB2)/RFB2
where RPAR is the parallel combination of RFB1 and RNR
.
Based on the component values shown in Figure 62, the
ADM7170 has the following characteristics:
V
EN
NO C
1nF
SS
•
•
•
•
•
DC gain of 5 (14 dB)
3 dB roll-off frequency of 0.8 Hz
High frequency ac gain of 1.09 (0.75 dB)
Noise reduction factor of 4.42 (12.91 dB)
RMS noise of the adjustable LDO without noise reduction
of 25 µV rms
4.7nF
10nF
0
1
2
3
4
5
6
7
8
9
10
TIME (ms)
Figure 61. Typical Soft Start Behavior, Different CSS Values
NOISE REDUCTION OF THE ADM7170 IN
ADJUSTABLE MODE
•
RMS noise of the adjustable LDO with noise reduction
(assuming 5 µV rms for fixed voltage option) of 5.5 µV rms
The ultralow output noise of the ADM7170 is achieved by
keeping the LDO error amplifier in unity gain and setting the
reference voltage equal to the output voltage. This architecture
does not work for an adjustable output voltage LDO in the
conventional sense. However, the ADM7170 architecture allows
any fixed output voltage to be set to a higher voltage with an
external voltage divider. For example, the adjustable (1.2 V in
unity gain) output ADM7170 can be set to a 6 V output
according to the following equation:
EFFECT OF NOISE REDUCTION ON START-UP TIME
The start-up time of the ADM7170 is affected by the noise
reduction network and must be considered in applications
wherein power supply sequencing is critical.
The noise reduction circuit adds a pole in the feedback loop
that slows down the start-up time. The start-up time for an
adjustable model with a noise reduction network can be
approximated using the following equation:
V
OUT = 1.2 V(1 + R1/R2)
SSNRTIME (sec) = 5.5 × CNR × (RNR + RFB1
)
The disadvantage of using the ADM7170 in this manner is that
the output voltage noise is proportional to the output voltage.
Therefore, it is best to choose a fixed output voltage that is close
to the target voltage to minimize the increase in output noise.
For a CNR, RNR, and RFB1 combination of 1 µF, 5 kΩ, and 200 kΩ,
respectively, as shown in Figure 62, the start-up time is
approximately 1.1 seconds. When SSNRTIME is greater than
SSTIME, it dictates the length of the start-up time instead of the
soft start capacitor.
The adjustable LDO circuit can be modified to reduce the
output voltage noise to levels close to that of the fixed output
ADM7170. The circuit shown in Figure 62 adds two additional
components to the output voltage setting resistor divider. CNR
and RNR are added in parallel with RFB1 to reduce the ac gain of
the error amplifier. RNR is chosen to be small with respect to
FB2. If RNR is 1% to 10% of the value of RFB2, the minimum ac
gain of the error amplifier is approximately 0.1 dB to 0.8 dB.
The actual gain is determined by the parallel combination of
CURRENT-LIMIT AND THERMAL OVERLOAD
PROTECTION
The ADM7170 is protected against damage due to excessive
power dissipation by current-limit and thermal overload
protection circuits. The ADM7170 is designed to current limit
when the output load reaches 3 A (typical). When the output
load exceeds 3 A, the output voltage is reduced to maintain a
constant current limit.
R
R
NR and RFB1. This ensures that the error amplifier always
operates at slightly greater than unity gain.
Rev. C | Page 19 of 23
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