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ADM5180 PDF预览

ADM5180

更新时间: 2024-02-01 17:46:27
品牌 Logo 应用领域
亚德诺 - ADI 驱动器
页数 文件大小 规格书
6页 104K
描述
Octal, RS-232/RS-423 Line Receiver

ADM5180 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:QLCC
包装说明:QCCJ,针数:28
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.29
输入特性:DIFFERENTIAL SCHMITT TRIGGER接口集成电路类型:LINE RECEIVER
接口标准:EIA-232-E; V.10; V.11; V.28; X.26; X.27; EIA-422-A; EIA-423-AJESD-30 代码:S-PQCC-J28
JESD-609代码:e3长度:11.505 mm
湿度敏感等级:3功能数量:1
端子数量:28最高工作温度:70 °C
最低工作温度:输出特性:TOTEM-POLE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:QCCJ封装形状:SQUARE
封装形式:CHIP CARRIER峰值回流温度(摄氏度):260
认证状态:Not Qualified最大接收延迟:550 ns
接收器位数:8座面最大高度:4.57 mm
最大压摆率:5 mA最大供电电压:5.25 V
最小供电电压:4.75 V标称供电电压:5 V
表面贴装:YES技术:BICMOS
温度等级:COMMERCIAL端子面层:Matte Tin (Sn)
端子形式:J BEND端子节距:1.27 mm
端子位置:QUAD处于峰值回流温度下的最长时间:40
宽度:11.505 mmBase Number Matches:1

ADM5180 数据手册

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a
Octal, RS-232/RS-423 Line Receiver  
ADM5180  
FUNCTIO NAL BLO CK D IAGRAM  
FEATURES  
Eight Differential Line Receivers in One Package  
Meets EIA Standard EIA-232E, 423A, 422A and  
CCITT V.10, V.11, V.28  
ADM5180  
Single +5 V Supply  
Differential Inputs Withstand ±25 V  
Internal Hysteresis  
A–  
A+  
A
A
B
C
D
O
O
Low Pow er CMOS –3.5 m A Supply Current  
TTL/ CMOS Com patible Outputs  
Available in 28-Pin DIP and PLCC Packages  
Low Pow er Replacem ent for UC5180C/ NE5180  
B–  
B+  
B
C–  
APPLICATIONS  
C
D
O
O
C+  
High Speed Com m unication  
Com puter I-O Ports  
Peripherals  
High Speed Modem s  
Printers  
D–  
D+  
FS1  
FS2  
E–  
Logic Level Translation  
E
E
F
GENERAL D ESCRIP TIO N  
O
E+  
T he ADM5180 is an octal differential line receiver suitable for a  
wide range of digital communication systems with data rates up to  
200 kB/s. Input signals conforming to EIA Standards 232-E, 422A  
and CCIT T V.10, V.11, V.28, X.26, and X.27 are accepted and  
translated into T T L /CMOS output signal levels.  
F–  
F+  
F
O
G–  
G+  
T he ADM5180 is a superior upgrade for the UC5180C and the  
NE5180. It is fabricated on an advanced BiCMOS process,  
allowing high speed bipolar circuitry to be combined with low  
power CMOS. T his minimizes the power consumption to less than  
25 mW.  
G
G
H
O
H–  
H+  
H
O
A failsafe function ensures a known output state under a variety of  
input fault conditions as defined in RS-422A and RS-423A. T he  
failsafe function is controlled by FS1 and FS2. Each controls four  
receivers. With FS = Low and a fault condition the output is forced  
low while if FS = High, the output is forced high.  
Truth Table  
D ifferential Input  
(+) - (–)  
Failsafe Input  
FS1, FS2  
Receiver  
Logic O utput  
T he device is available in both 28-pin DIP and 28-lead PLCC  
packages.  
>200 mV  
<200 mV  
O/C  
S/C  
O/C  
X
X
L
L
H
H
H
L
L
L
H
H
S/C  
REV. 0  
Inform ation furnished by Analog Devices is believed to be accurate and  
reliable. However, no responsibility is assum ed by Analog Devices for its  
use, nor for any infringem ents of patents or other rights of third parties  
which m ay result from its use. No license is granted by im plication or  
otherwise under any patent or patent rights of Analog Devices.  
One Technology Way, P.O. Box 9106, Norw ood. MA 02062-9106, U.S.A.  
Tel: 617/ 329-4700 Fax: 617/ 326-8703  

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