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ADM4853ACP

更新时间： 2024-11-25 20:52:03
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页数 文件大小 规格书
9页 260K
描述
IC LINE TRANSCEIVER, DSO8, LFCSP-8, Line Driver or Receiver

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ADM4853ACP 数据手册

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5V Slew Rate Limited Half and Full Duplex  
RS-485/RS-422 Transceivers  
Preliminary Technical Data  
ADM4850-ADM4857  
FUNCTIONAL BLOCK DIAGRAMS  
FEATURES  
EIA RS-485/RS-422 Compliant  
Data Rate Options  
ADM4850/ADM4854 – 115kbps  
ADM4851/ADM4855 – 500kbps  
ADM4852/ADM4856 – 2.5Mbps  
ADM4853/ADM4857 – 10Mbps  
Half and Full Duplex Options  
Reduced Slew Rates for Low EMI  
True Failsafe Receiver Inputs  
2µA (Max) Supply Current in Shutdown Mode  
Up to 256 Transceivers on a bus  
Outputs High-Z when Disabled or Powered-Off  
-7V to +12V Bus Common Mode Range  
Thermal Shutdown and Short Circuit Protection  
Pin Compatible with MAX308x  
V
V
CC  
CC  
ADM4850–ADM4853  
ADM4854–ADM4857  
RO  
R
A
B
RO  
DI  
R
A
B
RE  
DE  
Z
Y
D
D
DI  
GND  
GND  
Specified over –40°C to +85°C Temperature Range  
Available in 8-Lead SOIC and LFCSP Packages  
APPLICATIONS  
Low-Power RS-485 Applications  
EMI Sensitive Systems  
DTE-DCE Interfaces  
Industrial Control  
Packet Switching  
Local Area Networks  
Level Translators  
The driver outputs are slew rate limited in order to reduce EMI  
and data errors caused by reflections from improperly  
terminated buses. Excessive power dissipation caused by bus  
contention or by output shorting is prevented with a thermal  
shutdown circuit.  
The parts are fully specified over the commercial and industrial  
temperature ranges and are available in 8-lead SOIC and  
LFCSP packages  
GENERAL DESCRIPTION  
The ADM4850-ADM4857 are differential line transceivers  
suitable for high speed full and half duplex data communication  
on multipoint bus transmission lines. They are designed for  
balanced data transmission and comply with EIA Standards RS-  
485 and RS-422. The ADM4850-ADM4853 are half duplex  
transceivers which share differential lines and have separate  
enable inputs for the driver and receiver. The full duplex  
ADM4854-ADM4857 transceivers have dedicated differential  
line driver outputs and receiver inputs.  
Table 1. Selection Table  
The devices have a 1/8-unit-load receiver input impedance  
which allows up to 256 transceivers on a bus. Since only one  
driver should be enabled at any time, the output of a disabled or  
powered down driver is three-stated to avoid overloading the  
bus.  
Part No.  
Half/Full Duplex  
Data Rate  
115kbps  
500kbps  
2.5Mbps  
10Mbps  
115kbps  
500kbps  
2.5Mbps  
10Mbps  
ADM4850  
ADM4851  
ADM4852  
ADM4853  
ADM4854  
ADM4855  
ADM4856  
ADM4857  
Half  
Half  
Half  
Half  
Full  
Full  
Full  
Full  
The receiver inputs have a true failsafe feature which ensures a  
logic high output level when the inputs are open or shorted.  
This guarantees that the receiver outputs are in a known state  
before communication begins and when communication ceases.  
Rev. PrB  
Information furnished by Analog Devices is believed to be accurate and reliable.  
However, no responsibility is assumed by Analog Devices for its use, nor for any  
infringements of patents or other rights of third parties that may result from its use.  
Specifications subject to change without notice. No license is granted by implication  
or otherwise under any patent or patent rights of Analog Devices. Trademarks and  
registered trademarks are the property of their respective companies.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700  
Fax: 781.326.8703  
www.analog.com  
© 2004Analog Devices, Inc. All rights reserved.  
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