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ADM307EARZ

更新时间： 2024-11-18 03:56:55
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亚德诺 - ADI /
页数 文件大小 规格书
20页 623K
描述
3.3 V, 【15 kV ESD-Protected, Half- and Full-Duplex, RS-485/RS-422 Transceivers

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ADM307EARZ 数据手册

 浏览型号ADM307EARZ的Datasheet PDF文件第2页浏览型号ADM307EARZ的Datasheet PDF文件第3页浏览型号ADM307EARZ的Datasheet PDF文件第4页浏览型号ADM307EARZ的Datasheet PDF文件第5页浏览型号ADM307EARZ的Datasheet PDF文件第6页浏览型号ADM307EARZ的Datasheet PDF文件第7页 
3.3 V, ± ±1 ꢀV ꢁESD-Proteotꢂ, ꢃHalD Hꢄꢂ  
FuaaDSupatx, RED481/RED422 TPHꢄsetivtPs  
ASM3070ꢁ/ASM307±ꢁ/ASM3072ꢁ/ASM3073ꢁ/ASM3074ꢁ/ASM3071ꢁ/ASM3076ꢁ/ASM3077ꢁ/ASM3078ꢁ  
FEATURES  
FUNCTIONAL BLOCK DIAGRAMS  
V
TIA/EIA RS-485/RS-422 compliant  
CC  
15 kV ESD protection on RS-485 input/output pins  
Data rates  
ADM3070E/ADM3071E/ADM3072E: 250 kbps  
ADM3073E/ADM3074E/ADM3075E: 500 kbps  
ADM3076E/ADM3077E/ADM3078E: 16 Mbps  
Half- and full-duplex options  
ADM3070E/  
ADM3073E/  
ADM3076E  
A
R
RO  
B
RE  
DE  
True fail-safe receiver inputs  
Up to 256 nodes on the bus  
Z
Y
DI  
D
−40°C to +125°C temperature option  
Hot-swap input structure on DE and RE pins  
Reduced slew rates for low EMI  
GND  
Figure 1.  
Low power shutdown current (all except  
ADM3071E/ADM3074E/ADM3077E)  
Outputs high-Z when disabled or powered off  
Common-mode input range: −7 V to +12 V  
Thermal shutdown and short-circuit protection  
8-lead and 14-lead narrow SOIC packages  
V
CC  
ADM3071E/  
ADM3074E/  
ADM3077E  
A
B
R
RO  
DI  
APPLICATIONS  
Z
Y
Power/energy metering  
Industrial control  
Lighting systems  
D
GND  
.
Telecommunications  
Security systems  
Figure 2.  
V
Instrumentation  
CC  
ADM3072E/  
ADM3075E/  
ADM3078E  
GENERAL DESCRIPTION  
The ADM3070E to ADM3078E are 3.3 V, low power data  
transceivers with ±±1 ꢀV ESD protection suitable for full- and  
half-duplex communication on multipoint bus transmission  
lines. They are designed for balanced data transmission, and they  
comply with TIA/EIA standards RS-481 and RS-422.  
R
RO  
RE  
DE  
A
B
DI  
D
The devices have an ⅛ unit load receiver input impedance,  
which allows up to 216 transceivers on a bus. Because only one  
driver should be enabled at any time, the output of a disabled or  
powered-down driver is tristated to avoid overloading the bus.  
GND  
Figure 3.  
The receiver inputs have a true fail-safe feature, which  
eliminates the need for external bias resistors and ensures a  
logic high output level when the inputs are open or shorted.  
This guarantees that the receiver outputs are in a ꢀnown state  
before communication begins and when communication ceases.  
(continued on Page 3)  
Rev. A  
Information furnished by Analog Devices is believed to be accurate and reliable. However, no  
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other  
rights of third parties that may result from its use. Specifications subject to change without notice. No  
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.  
Trademarks and registeredtrademarks arethe property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700  
Fax: 781.461.3113  
www.analog.com  
©2006 Analog Devices, Inc. All rights reserved.  
 
 
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