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ADM1087

更新时间： 2024-01-14 07:10:40
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
16页 360K
描述
Simple Sequencers in 6-Lead SC70

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ADM1087 技术参数

是否无铅：含铅是否Rohs认证：不符合
生命周期：Obsolete零件包装代码：TSSOP
包装说明：MO-203AB, PLASTIC, SC70-6针数：6
Reach Compliance Code：not_compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.33
Is Samacsys：N可调阈值：YES
模拟集成电路 - 其他类型：POWER SUPPLY SUPPORT CIRCUITJESD-30 代码：R-PDSO-G6
JESD-609代码：e0长度：2 mm
信道数量：1功能数量：1
端子数量：6最高工作温度：125 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装等效代码：TSSOP6,.08
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：220电源：2.5/3.3 V
认证状态：Not Qualified座面最大高度：1.1 mm
子类别：Power Management Circuits最大供电电流 (Isup)：0.02 mA
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：2.25 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：AUTOMOTIVE
端子面层：Tin/Lead (Sn85Pb15)端子形式：GULL WING
端子节距：0.65 mm端子位置：DUAL
处于峰值回流温度下的最长时间：30宽度：1.25 mm
Base Number Matches：1

ADM1087 数据手册

 浏览型号ADM1087的Datasheet PDF文件第6页浏览型号ADM1087的Datasheet PDF文件第7页浏览型号ADM1087的Datasheet PDF文件第8页浏览型号ADM1087的Datasheet PDF文件第10页浏览型号ADM1087的Datasheet PDF文件第11页浏览型号ADM1087的Datasheet PDF文件第12页 
ADM1085/ADM1086/ADM1087/ADM1088  
CIRCUIT INFORMATION  
When VIN reaches the upper threshold voltage (VTH_RISING), an  
internal circuit generates a delay (tEN) before the enable output  
is asserted. If VIN drops below the lower threshold voltage  
(VTH_FALLING), the enable output is deasserted immediately.  
TIMING CHARACTERISTICS AND TRUTH TABLES  
The enable outputs of the ADM1085/ADM1086/ADM1087/  
ADM1088 are related to the VIN and enable inputs by a simple  
AND function. The enable output is asserted only if the enable  
input is asserted and the voltage at VIN is above VTH_RISING, with  
the time delay elapsed. Table 5 and Table 6 show the enable  
output logic states for different VIN/enable input combinations  
when the capacitor delay has elapsed. The timing diagrams in  
Figure 18 and Figure 19 give a graphical representation of how  
the ADM1085/ADM1086/ADM1087/ADM1088 enable outputs  
respond to VIN and enable input signals.  
Similarly, if the enable input is disabled while VIN is above the  
threshold, the enable output deasserts immediately. Unlike VIN, a  
ENIN  
low-to-high transition on ENIN (or high-to-low on  
ENOUT  
) does  
not yield a time delay on ENOUT (  
).  
CAPACITOR-ADJUSTABLE DELAY CIRCUIT  
Figure 20 shows the internal circuitry used to generate the time  
delay on the enable output. A 250 nA current source charges a  
small internal parasitic capacitance, CINT. When the capacitor  
voltage reaches 1.2 V, the enable output is asserted. The time  
taken for the capacitor to reach 1.2 V, in addition to the propa-  
gation delay of the comparator, constitutes the enable timeout,  
which is typically 35 µs.  
Table 5. ADM1085/ADM1086 Truth Table  
VIN  
ENIN  
ENOUT  
<VTH_FALLING  
<VTH_FALLING  
>VTH_RISING  
>VTH_RISING  
0
1
0
1
0
0
0
1
To minimize the delay between VIN falling below VTH_FALLING and  
the enable output de-asserting, an NMOS transistor is con-  
nected in parallel with CINT. The output of the voltage detector  
is connected to the gate of this transistor so that, when VIN falls  
below VTH_FALLING, the transistor switches on and CINT discharges  
quickly.  
Table 6. ADM1087/ADM1088 Truth Table  
ENIN  
ENOUT  
VIN  
<VTH_FALLING  
<VTH_FALLING  
>VTH_RISING  
>VTH_RISING  
1
0
1
0
1
1
1
0
V
CC  
250nA  
SIGNAL FROM  
VOLTAGE  
DETECTOR  
TO AND GATE  
AND OUTPUT  
STAGE  
V
V
V
TH_FALLING  
C
IN  
TH_RISING  
1.2V  
INT  
CEXT  
C
ENIN  
Figure 20. Capacitor-Adjustable Delay Circuit  
tEN  
Figure 18. ADM1085/ADM1086 Timing Diagram  
ENOUT  
Connecting an external capacitor to the CEXT pin delays the  
rise time—and therefore the enable timeout—further. The  
relationship between the value of the external capacitor and the  
resulting timeout is characterized by the following equation:  
V
V
V
TH_FALLING  
IN  
TH_RISING  
t
EN = (C × 4.8 ×106) + 35 µs  
ENIN  
tEN  
ENOUT  
Figure 19. ADM1087/ADM1088 Timing Diagram  
Rev. 0 | Page 9 of 16  
 
 
 
 
 
 
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