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ADL5391ACPZ-WP PDF预览

ADL5391ACPZ-WP

更新时间: 2024-02-21 19:36:11
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
16页 430K
描述
DC to 2.0 GHz Multiplier

ADL5391ACPZ-WP 技术参数

是否无铅: 含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:QFN
包装说明:HVQCCN,针数:16
Reach Compliance Code:compliantECCN代码:5A991.B
HTS代码:8542.39.00.01风险等级:5.09
JESD-30 代码:S-XQCC-N16JESD-609代码:e3
长度:3 mm湿度敏感等级:3
功能数量:1端子数量:16
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:UNSPECIFIED封装代码:HVQCCN
封装形状:SQUARE封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度(摄氏度):260认证状态:Not Qualified
座面最大高度:0.9 mm标称供电电压:5 V
表面贴装:YES技术:BIPOLAR
电信集成电路类型:TELECOM CIRCUIT温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn)端子形式:NO LEAD
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:40宽度:3 mm
Base Number Matches:1

ADL5391ACPZ-WP 数据手册

 浏览型号ADL5391ACPZ-WP的Datasheet PDF文件第9页浏览型号ADL5391ACPZ-WP的Datasheet PDF文件第10页浏览型号ADL5391ACPZ-WP的Datasheet PDF文件第11页浏览型号ADL5391ACPZ-WP的Datasheet PDF文件第13页浏览型号ADL5391ACPZ-WP的Datasheet PDF文件第14页浏览型号ADL5391ACPZ-WP的Datasheet PDF文件第15页 
ADL5391  
0
–5  
be removed through calibration. Figure ±0 shows the response  
of the ADL5391 as a square law detector, Figure ±1 shows the  
error vs. the input power, and Figure ±± shows the  
configuration used.  
BLEEDTHRU GAIN  
–10  
–15  
–20  
–25  
–30  
–35  
–40  
–45  
–50  
–55  
–60  
–65  
SECOND HARMONIC GAIN  
0.7  
0.6  
0.5  
0.4  
0.3  
0.2  
0.1  
0
THIRD HARMONIC GAIN  
10 100 200 300 400 500 600 700 800 900 1000  
FREQUENCY (MHz)  
Figure 18. Single-Ended (DC) ADL5391 Used as a Harmonic Generator  
53  
XM  
XP  
YM  
10dB PAD  
5dB PAD  
150Ω  
21Ω  
0
0.1  
0.2  
0.3  
0.4  
0.5  
0.6  
0.7  
0.8  
XIN  
WP  
WM  
2
V
(V rms)  
IN  
62Ω  
74Ω  
Figure 20. ADL5391 Used as Square Law Detector DC Output vs. Square of Input  
53YIN  
21Ω  
200Ω  
YP  
1.6  
1.4  
1.2  
1.0  
0.8  
0.6  
0.4  
0.2  
0
74Ω  
5dB PAD  
Figure 19. Setup for Single-Ended Data  
Use as a Detector  
The ADL5391 can be used as a square law detector. When  
amplitude squaring is performed, there are components of the  
multiplier output that correlate to the signal bleedthrough and  
second harmonic, as seen in Equation 4. However, as noted in  
the Squaring and Frequency Doubling section, there is also a dc  
component that is directly related to the offset and the squared  
input magnitude. If a signal is split and feed into the X and Y  
inputs and a low-pass filter were place on the output, the resulting  
dc signal would be directly related to the square of the input  
magnitude. The intercept of the response will shift slightly from  
part to part (and over temperature) with the offset, but this can  
–0.2  
–30  
–25  
–20  
–15  
–10  
–5  
0
5
10  
PIN X (dBm)  
Figure 21. ADL5391Used as a Square Law Detector Error vs. Power Input  
C7  
0.1µF  
J6  
11  
12  
XM  
XP  
YP  
R2  
T3  
T2  
TC1-1-13M  
TC1-1-13M  
R6  
24.9  
56.2Ω  
T1  
74µH  
J2  
WM  
6
5
C18  
WP  
40µH  
40µH  
0.1µF  
R4  
100Ω  
R12  
OPEN  
45nF  
40nF  
74µH  
C4  
0.1µF  
J1  
WP  
WM  
R5  
24.9Ω  
J8  
XP  
YM  
YP  
13  
14  
R1  
56.2Ω  
C20  
0.1µF  
Figure 22. Schematic for ADL5391 Used as Square Law Detector  
Rev. 0 | Page 12 of 16  
 
 
 
 
 

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