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ADL5390ACPZ-WP PDF预览

ADL5390ACPZ-WP

更新时间: 2024-02-10 05:09:04
品牌 Logo 应用领域
罗彻斯特 - ROCHESTER 电信电信集成电路
页数 文件大小 规格书
25页 1769K
描述
SPECIALTY TELECOM CIRCUIT, QCC24, 4 X 4 MM, LEAD FREE, MO-220-VGGD-2, LFCSP-24

ADL5390ACPZ-WP 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:QFN
包装说明:HVQCCN,针数:24
Reach Compliance Code:unknown风险等级:5.67
JESD-30 代码:S-XQCC-N24JESD-609代码:e3
长度:4 mm湿度敏感等级:3
功能数量:1端子数量:24
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:UNSPECIFIED封装代码:HVQCCN
封装形状:SQUARE封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度(摄氏度):260认证状态:COMMERCIAL
座面最大高度:1 mm标称供电电压:5 V
表面贴装:YES技术:BIPOLAR
电信集成电路类型:TELECOM CIRCUIT温度等级:INDUSTRIAL
端子面层:MATTE TIN端子形式:NO LEAD
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:40宽度:4 mm
Base Number Matches:1

ADL5390ACPZ-WP 数据手册

 浏览型号ADL5390ACPZ-WP的Datasheet PDF文件第17页浏览型号ADL5390ACPZ-WP的Datasheet PDF文件第18页浏览型号ADL5390ACPZ-WP的Datasheet PDF文件第19页浏览型号ADL5390ACPZ-WP的Datasheet PDF文件第21页浏览型号ADL5390ACPZ-WP的Datasheet PDF文件第22页浏览型号ADL5390ACPZ-WP的Datasheet PDF文件第23页 
ADL5390  
EVALUATION BOARD  
The evaluation board circuit schematic for the ADL5390 is  
shown in Figure 44.  
The baseband input of the ADL5390 requires a differential volt-  
age drive. The evaluation board is set up to allow such a drive  
by connecting the differential voltage source to QBBP and  
QBBM. The common-mode voltage should be maintained at  
approximately 0.5 V. For this configuration, Jumpers W1 to W4  
should be removed.  
The evaluation board is configured to be driven from a  
single-ended 50 Ω source. Although the input of the ADL5390  
is differential, it may be driven single-ended with no loss of  
performance.  
The baseband input of the evaluation board may also be driven  
with a single-ended voltage. In this case, a bias level is provided  
to the unused input from Potentiometer R10 by installing either  
W1 or W2.  
The low-pass corner frequency of the baseband I and Q chan-  
nels can be reduced by installing capacitors in the C11 and C12  
positions. The low-pass corner frequency for either channel is  
approximated by  
Setting SW1 in Position B disables the ADL5390 output amplifier.  
With SW1 set to Position A, the output amplifier is enabled. With  
SW1 set to Position A, an external voltage signal, such as a pulse,  
can be applied to the DSOP SMA connector to exercise the  
output amplifier enable/disable function.  
45 kHz ×10 nF  
f3 dB  
Cexternal + 0.5 pF  
On this evaluation board, the I and Q baseband circuits are  
identical to each other, so the following description applies to  
each. The connections and circuit configuration for the I/Q  
baseband inputs are described in Table 4.  
Rev. 0 | Page 19 of 24  
 
 

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