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ADGS1412 PDF预览

ADGS1412

更新时间: 2024-02-20 06:15:29
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
26页 722K
描述
Serially Controlled, 1.5 Ω, On-Resistance, High Voltage, iCMOS, Quad SPST Switch

ADGS1412 技术参数

是否无铅: 含铅是否Rohs认证: 符合
生命周期:Active包装说明:HVQCCN,
针数:24Reach Compliance Code:compliant
风险等级:2.28Samacsys Description:RF Switch Quad SPST LFCSP-24
模拟集成电路 - 其他类型:SPDTJESD-30 代码:S-XQCC-N24
JESD-609代码:e3长度:4 mm
湿度敏感等级:3负电源电压最大值(Vsup):-16.5 V
负电源电压最小值(Vsup):-4.5 V标称负供电电压 (Vsup):-5 V
信道数量:1功能数量:4
端子数量:24通态电阻匹配规范:0.13 Ω
最大通态电阻 (Ron):4 Ω最高工作温度:125 °C
最低工作温度:-40 °C封装主体材料:UNSPECIFIED
封装代码:HVQCCN封装形状:SQUARE
封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度(摄氏度):260
座面最大高度:1 mm最大供电电压 (Vsup):16.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:AUTOMOTIVE端子面层:Matte Tin (Sn)
端子形式:NO LEAD端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
宽度:4 mmBase Number Matches:1

ADGS1412 数据手册

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Serially Controlled, 1.5 Ω, On-Resistance,  
High Voltage, iCMOS, Quad SPST Switch  
ADGS1412  
Data Sheet  
FEATURES  
FUNCTIONAL BLOCK DIAGRAMS  
SPI interface with error detection  
ADGS1412  
Includes CRC, invalid read/write address, and SCLK count  
error detection  
Supports burst and daisy-chain mode  
Industry-standard SPI Mode 0 and Mode 3 interface-  
compatible  
S1  
S2  
S3  
S4  
D1  
D2  
D3  
D4  
1.5 Ω typical on resistance at 25°C  
0.3 Ω typical on-resistance flatness at 25°C  
0.1 Ω typical on-resistance match between channels at 25°C  
Fully specified at 15 V, 5 V, and +12 V  
SPI  
INTERFACE  
SDO  
V
SS to VDD analog signal range  
SCLK SDI CS RESET/V  
L
APPLICATIONS  
Figure 1.  
Automated test equipment  
Data acquisition systems  
Battery-powered systems  
Sample-and-hold systems  
Audio signal routing  
Video signal routing  
Communications systems  
Relay replacement  
GENERAL DESCRIPTION  
The ADGS1412 contains four independent single-pole/single-  
throw (SPST) switches. An serial peripheral interface (SPI)  
controls the switches. The SPI interface has robust error detection  
features such as cyclic redundancy check (CRC) error detection,  
invalid read/write address detection, and SCLK count error  
detection.  
PRODUCT HIGHLIGHTS  
1. SPI interface removes the need for parallel conversion,  
logic traces and reduces GPIO channel count.  
2. Daisy-chain mode removes additional logic traces when  
multiple devices are used.  
3. CRC error detection, invalid read/write address detection,  
and SCLK count error detection ensures a robust digital  
interface.  
It is possible to daisy-chain multiple ADGS1412 devices together.  
Daisy-chain mode enables the configuration of multiple devices  
with a minimal amount of digital lines. The ADGS1412 can also  
operate in burst mode to decrease the time between SPI  
commands.  
4. Safety integrity level (SIL)-compatible.  
5. Minimum distortion.  
iCMOS construction ensures ultralow power dissipation, making  
the device ideally suited for portable and battery-powered  
instruments.  
Each switch conducts equally well in both directions when on,  
and each switch has an input signal range that extends to the  
supplies. In the off condition, signal levels up to the supplies  
are blocked.  
The on-resistance profile is flat over the full analog input range,  
which ensures good linearity and low distortion when switching  
audio signals.  
Rev. 0  
Document Feedback  
Information furnished by Analog Devices is believed to be accurate and reliable. However, no  
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other  
rights of third parties that may result from its use. Specifications subject to change without notice. No  
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.  
Trademarks and registeredtrademarks arethe property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700  
Technical Support  
©2016 Analog Devices, Inc. All rights reserved.  
www.analog.com  
 
 
 
 
 

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