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ADGS1414DBCCZ PDF预览

ADGS1414DBCCZ

更新时间: 2024-02-17 00:24:03
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
28页 552K
描述
SPI, 1.5 Ω RON, ±15 V/±5 V/12 V, High Density Octal SPST Switch

ADGS1414DBCCZ 数据手册

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SPI, 1.5 Ω RON, 15 V/ 5 V/+12 V, High  
Density Octal SPST Switch  
Data Sheet  
ADGS1414D  
FEATURES  
FUNCTIONAL BLOCK DIAGRAM  
V
V
SS  
DD  
SPI with error detection  
Includes CRC, invalid read and write address, and SCLK  
count error detection  
ADGS1414D  
Supports burst mode and daisy-chain mode  
Industry-standard SPI Mode 0 and Mode 3 interface  
compatible  
S1  
S2  
S3  
S4  
S5  
S6  
S7  
D1  
D2  
D3  
D4  
D5  
D6  
D7  
Integrated passive components  
Route through of digital signals and supplies  
Guaranteed break-before-make switching allowing external  
wiring of switches to deliver multiplexer configurations  
1.5 Ω typical on resistance at 25°C ( 15 V dual supply)  
0.3 Ω typical on resistance flatness at 25°C ( 15 V dual supply)  
0.1 Ω typical on resistance match between channels at 25°C  
( 15 V dual supply)  
S8  
D8  
V
L
SPI  
INTERFACE  
SDO  
V
SS to VDD analog signal range  
Fully specified at 15 V, 5 V, and +12 V  
SCLK SDI CS RESET/V  
L
1.8 V logic compatibility with 2.7 V ≤ VL ≤ 3.3 V (excludes SPI  
readback to a 1.8 V device)  
4 mm × 5 mm, 30-terminal LGA  
Figure 1.  
The ADGS1414D is suited to high density switching  
applications, such as large switching matrices and fanout  
applications.  
APPLICATIONS  
Automated test equipment  
Data acquisition systems  
Sample-and-hold systems  
Audio and video signal routing  
Communications systems  
Relay replacement  
Each switch conducts equally well in both directions when on,  
and each switch has an input signal range that extends to the  
supplies. In the off condition, signal levels up to the supplies  
are blocked.  
Multifunction pin names may be referenced by their relevant  
function only.  
GENERAL DESCRIPTION  
PRODUCT HIGHLIGHTS  
The ADGS1414D contains eight independent SPST switches. A  
serial peripheral interface (SPI) controls the switches. The SPI  
has robust error detection features, such as cyclic redundancy  
check (CRC) error detection, invalid read and write address  
detection, and SCLK count error detection.  
1. The SPI removes the need for parallel conversion and logic  
traces and reduces the general-purpose input and output  
(GPIO) channel count.  
2. Daisy-chain mode removes additional logic traces when  
multiple devices are used.  
It is possible to daisy-chain multiple ADGS1414D devices  
together. Daisy-chain mode enables the configuration of  
multiple devices with a minimal amount of digital lines. The  
route of digital signals and supplies through the ADGS1414D  
allows for a further increase in channel density. Integrated  
passive components eliminate the need for external passive  
components.  
3. Route through of digital signals and supplies eases routing  
and allows for an increase in channel density.  
4. Integrated passive components eliminate the need for  
external passive components.  
5. CRC error detection, invalid read and write address  
detection, and SCLK count error detection ensure a robust  
digital interface.  
6. CRC, invalid read and write address, and SCLK error  
detection capabilities allow for the use of the ADGS1414D  
in safety critical systems.  
7. Minimum distortion.  
Rev. 0  
Document Feedback  
Information furnished by Analog Devices is believed to be accurate and reliable. However, no  
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other  
rights of third parties that may result from its use. Specifications subject to change without notice.  
No license is granted by implication or otherwise under any patent or patent rights of Analog  
Devices. Trademarks and registeredtrademarks are the property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700  
Technical Support  
©2020 Analog Devices, Inc. All rights reserved.  
www.analog.com  
 
 
 
 
 

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