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ADF7021BCPZ PDF预览

ADF7021BCPZ

更新时间: 2024-01-08 22:35:15
品牌 Logo 应用领域
亚德诺 - ADI ISM频段
页数 文件大小 规格书
44页 462K
描述
High Performance Narrowband ISM Transceiver IC

ADF7021BCPZ 技术参数

是否无铅: 含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:QFN
包装说明:HVQCCN, LCC48,.27SQ,20针数:48
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.16
JESD-30 代码:S-XQCC-N48JESD-609代码:e3
长度:7 mm湿度敏感等级:1
功能数量:1端子数量:48
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:UNSPECIFIED封装代码:HVQCCN
封装等效代码:LCC48,.27SQ,20封装形状:SQUARE
封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度(摄氏度):225
电源:2.5/3.3 V认证状态:Not Qualified
座面最大高度:1 mm子类别:Other Telecom ICs
标称供电电压:3 V表面贴装:YES
电信集成电路类型:RF AND BASEBAND CIRCUIT温度等级:INDUSTRIAL
端子面层:MATTE TIN端子形式:NO LEAD
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:7 mm
Base Number Matches:1

ADF7021BCPZ 数据手册

 浏览型号ADF7021BCPZ的Datasheet PDF文件第38页浏览型号ADF7021BCPZ的Datasheet PDF文件第39页浏览型号ADF7021BCPZ的Datasheet PDF文件第40页浏览型号ADF7021BCPZ的Datasheet PDF文件第41页浏览型号ADF7021BCPZ的Datasheet PDF文件第43页浏览型号ADF7021BCPZ的Datasheet PDF文件第44页 
ADF7021  
Preliminary Technical Data  
REGISTER 15—TEST MODE REGISTER  
ANALOG TEST  
MODES  
PLL TEST  
MODES  
PFD/CP TEST  
MODES  
Σ-Δ TEST  
MODES  
Tx TEST  
MODES  
Rx TEST  
MODES  
ADDRESS  
BITS  
CLK MUX  
CAL OVERRIDE  
0
1
2
3
AUTO CAL  
OVERRIDE GAIN  
OVERRIDE BW  
PFD/CP TEST MODES  
0
1
2
3
4
5
6
7
DEFAULT, NO BLEED  
(+VE) CONSTANT BLEED  
(–VE) CONSTANT BLEED  
(–VE) PULSED BLEED  
(–VE) PULSE BLD, DELAY UP?  
CP PUMP UP  
OVERRIDE BW AND GAIN  
REG1 PD  
0
1
NORMAL  
PWR DWN  
CP TRI-STATE  
CP PUMP DN  
FORCE LD HIGH  
Σ-Δ TEST MODES  
0
1
NORMAL  
FORCE  
0
1
2
3
4
5
6
7
DEFAULT, 3RD ORDER SD, NO DITHER  
1ST ORDER SD  
2ND ORDER SD  
DITHER TO FIRST STAGE  
DITHER TO SECOND STAGE  
DITHER TO THIRD STAGE  
DITHER × 8  
ANALOG TEST MODES  
0
1
2
3
4
5
6
7
8
9
BAND GAP VOLTGE  
40µA CURRENT FROM REG4  
FILTER I CHANNEL: STAGE 1  
FILTER I CHANNEL: STAGE 2  
FILTER I CHANNEL: STAGE 1  
FILTER Q CHANNEL: STAGE 1  
FILTER Q CHANNEL: STAGE 2  
FILTER Q CHANNEL: STAGE 1  
ADC REFERENCE VOLTAGE  
BIAS CURRENT FROM RSSI 5µA  
DITHER × 32  
Tx TEST MODES  
0
1
2
3
4
5
6
NORMAL OPERATION  
Tx CARRIER ONLY  
Tx +VE TONE ONLY  
Tx –VE TONE ONLY  
Tx "1010" PATTERN  
Tx PN9 DATA, AT PROGRAMMED RATE  
Tx SYNC BYTE REPEATEDLY  
10 FILTER COARSE CAL OSCILLATOR O/P  
11 ANALOG RSSI I CHANNEL  
12 OSET LOOP +VE FBACK V (I CH)  
13 SUMMED O/P OF RSSI RECTIFIER+  
14 SUMMED O/P OF RSSI RECTIFIER–  
15 BIAS CURRENT FROM BB FILTER  
Rx TEST MODES  
NORMAL  
SCLK, SDATA -> I, Q  
REVERSE I, Q  
DDT SLICER ON RxDATA  
T/4 SLICER ON RxDATA  
3FSK SLICER ON RxDATA  
I, Q TO Rx CLK, RxDATA  
SDATA TO CDR  
0
1
2
3
4
5
6
7
8
9
PLL TEST MODES  
0
1
2
3
4
5
6
7
8
9
NORMAL OPERATION  
R DIV  
N DIV  
RCNTR/2 ON MUXOUT  
NCNTR/2 ON MUXOUT  
ACNTR TO MUXOUT  
PFD PUMP UP TO MUXOUT  
PFD PUMP DN TO MUXOUT  
SDATA TO MUXOUT (OR SREAD?)  
ADDITIONAL FILTERING ON I, Q  
ENABLE REG 14 DEMOD PARAMETERS  
10 POWER DOWN DDT AND ED IN T/4 MODE  
11 ENVELOPE DETECTOR WATCHDOG DISABLED  
12 3FSK PREMABLE DETECT ON RxDATA  
13 PROHIBIT CALACTIVE  
14 FORCE CALACTIVE  
15 ENABLE DEMOD DURING CAL  
ANALOG LOCK DETECT ON MUXOUT  
10 END OF COARSE CAL ON MUXOUT  
11 END OF FINE CAL ON MUXOUT  
FORCE NEW PRESCALER CONFIG.  
FOR ALL N  
13 TEST MUX SELECTS DATA  
12  
14 LOCK DETECT PRECISION  
15 NEG PD POLARITY-*NOT SUPPORTED*  
CLK MUXES  
0
1
2
3
4
5
6
7
NORMAL, NO OUTPUT  
DEMOD_CLK  
CDR_CLK  
SEQ_CLK  
BB_OFFSET CLK  
SIGMA_DELTA CLK  
ADC_CLK  
Tx/Rx CLK  
Figure 47.  
Rev. PrI | Page 42 of 44  

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