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ADF4219L PDF预览

ADF4219L

更新时间: 2024-02-22 22:01:16
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描述
ADF4217L/18L/19L: Dual Low Power Frequency Synthesizers Data Sheet (Rev. B. 7/02)

ADF4219L 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:TSSOP包装说明:MO-153AC, TSSOP-20
针数:20Reach Compliance Code:not_compliant
ECCN代码:5A991.BHTS代码:8542.39.00.01
风险等级:5.92其他特性:ALSO REQUIRES A 3V TO 5.5V SUPPLY
模拟集成电路 - 其他类型:PLL FREQUENCY SYNTHESIZERJESD-30 代码:R-PDSO-G20
JESD-609代码:e0长度:6.5 mm
湿度敏感等级:1功能数量:1
端子数量:20最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP20,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):240电源:3/5,3 V
认证状态:Not Qualified座面最大高度:1.2 mm
子类别:PLL or Frequency Synthesis Circuits最大供电电压 (Vsup):3.3 V
最小供电电压 (Vsup):2.6 V标称供电电压 (Vsup):3 V
表面贴装:YES温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn85Pb15)端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:4.4 mm
Base Number Matches:1

ADF4219L 数据手册

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ADF4217L/ADF4218L/ADF4219L  
6
4
V
= 5V  
= 4mA  
P
I
CP  
2
0
–2  
–4  
–6  
0
0.5  
1.0  
1.5  
2.0  
2.5  
– V  
3.0  
3.5  
4.0  
4.5  
5.0  
V
CP  
TPC 13. Charge Pump Output Characteristics  
CIRCUIT DESCRIPTION  
Reference Input Section  
Prescaler  
The dual modulus prescaler (P/P + 1), along with the A and  
B counters, enables the large division ratio, N, to be realized  
(N = BP + A). This prescaler, operating at CML levels, takes  
the clock from the IF/RF input stage and divides it down to a  
manageable frequency for the CMOS A and B counters. It is  
based on a synchronous 4/5 core.  
The Reference Input stage is shown in Figure 2. SW1 and SW2  
are normally-closed switches. SW3 is normally open. When  
power-down is initiated, SW3 is closed and SW1 and SW2 are  
opened. This ensures that there is no loading of the REFIN pin  
on power-down.  
The prescaler is selectable. On the IF side, it can be set to either 8/9  
(DB20 of the IF AB Counter Latch set to 0) or 16/17 (DB20 set  
to 1). On the RF side of the ADF4217L/ADF4218L, it can be set  
to 64/65 or 32/33. On the ADF4219L, the RF prescaler can be  
set to 16/17 or 32/33. See Tables V, VI, VIII, and IX.  
POWER-DOWN  
CONTROL  
50k  
NC  
SW2  
REF  
IN  
NC  
TO R  
BUFFER  
A AND B COUNTERS  
COUNTER  
SW1  
The A and B CMOS counters combine with the dual modulus  
prescaler to allow a wide ranging division ratio in the PLL feed-  
back counter. The devices are guaranteed to work when the  
prescaler output is 188 MHz or less. Typically they will work  
with 250 MHz output from the prescaler.  
SW3  
NO  
NC = NORMALLY CLOSED  
NO = NORMALLY OPEN  
Figure 2. Reference Input Stage  
IF/RF Input Stage  
The IF/RF input stage is shown in Figure 3. It is followed by a  
two-stage limiting amplifier to generate the CML clock levels  
needed for the prescaler.  
N = BP + A  
TO PFD  
11(13)-BIT  
B COUNTER  
LOAD  
1.6V  
PRESCALER  
P/P+1  
BIAS  
FROM IF/RF  
LOAD  
GENERATOR  
INPUT STAGE  
AV  
DD  
6(5)-BIT  
MODULUS  
CONTROL  
A COUNTER  
500  
500⍀  
RF  
RF  
A
B
IN  
Figure 4. Reference Input Stage. A and B Counters  
IN  
AGND  
Figure 3. IF/RF Input Stage  
REV. B  
–9–  

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