Datasheet > ADF4219L

ADF4219L

更新时间： 2024-02-27 18:36:50

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ADF4217L/18L/19L: Dual Low Power Frequency Synthesizers Data Sheet (Rev. B. 7/02)

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ADF4219L 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	TSSOP	包装说明：	MO-153AC, TSSOP-20
针数：	20	Reach Compliance Code：	not_compliant
ECCN代码：	5A991.B	HTS代码：	8542.39.00.01
风险等级：	5.92	其他特性：	ALSO REQUIRES A 3V TO 5.5V SUPPLY
模拟集成电路 - 其他类型：	PLL FREQUENCY SYNTHESIZER	JESD-30 代码：	R-PDSO-G20
JESD-609代码：	e0	长度：	6.5 mm
湿度敏感等级：	1	功能数量：	1
端子数量：	20	最高工作温度：	85 °C
最低工作温度：	-40 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	TSSOP	封装等效代码：	TSSOP20,.25
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：	240	电源：	3/5,3 V
认证状态：	Not Qualified	座面最大高度：	1.2 mm
子类别：	PLL or Frequency Synthesis Circuits	最大供电电压 (Vsup)：	3.3 V
最小供电电压 (Vsup)：	2.6 V	标称供电电压 (Vsup)：	3 V
表面贴装：	YES	温度等级：	INDUSTRIAL
端子面层：	Tin/Lead (Sn85Pb15)	端子形式：	GULL WING
端子节距：	0.65 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	30	宽度：	4.4 mm
Base Number Matches：	1

ADF4219L 数据手册

ADF4217L/ADF4218L/ADF4219L

The A and B counters, in conjunction with the dual modulus

prescaler, make it possible to generate output frequencies that

are spaced only by the Reference Frequency divided by R. The

equation for the VCO frequency is as follows:

MUXOUT AND LOCK DETECT

The output multiplexer on the ADF4217L family allows the user

to access various internal points on the chip. The state of MUXOUT

is controlled by P3, P4, P11, and P12. See Tables IV and VII.

Figure 6 shows the MUXOUT section in block diagram form.

f_VCO= P ¥ B + A ¥ f

/ R

(

)

[

]

REFIN

f_VCO= Output frequency of external voltage controlled oscillator

(VCO).

= Preset modulus of dual modulus prescaler (8/9, 16/17, and

so on).

IF ANALOG LOCK DETECT

IF R COUNTER OUTPUT

= Preset Divide Ratio of binary 11-bit counter (ADF4217L/

ADF4218L), binary 13-bit counter (ADF4219L).

IF N COUNTER OUTPUT

MUXOUT

MUX

CONTROL

IF/RF ANALOG LOCK DETECT

RF R COUNTER OUTPUT

RF N COUNTER OUTPUT

RF ANALOG LOCK DETECT

= Preset Divide Ratio of binary 6-bit A counter (ADF4217L/

ADF4218L), binary 5-bit counter (ADF4219L).

_REFIN= Output frequency of the external reference frequency

oscillator.

= Preset divide ratio of binary 14-bit programmable reference

counter (1 to 16383). The ADF4219L has an R divide

of 15 bits.

DGND

Figure 6. MUXOUT Circuit

Lock Detect

R COUNTER

MUXOUT can be programmed for analog lock detect. The

N-channel open-drain analog lock detect should be operated

with an external pull-up resistor of 10 kW nominal. When lock

has been detected, it is high with narrow low-going pulses.

The 14-bit R counter allows the input reference frequency to be

divided down to produce the reference clock to the phase frequency

detector (PFD). Division ratios from 1 to 16,383 are allowed. The

extra R15 bit on the ADF4219L allows ratios from 1 to 32767.

INPUT SHIFT REGISTER

PHASE FREQUENCY DETECTOR (PFD) AND

CHARGE PUMP

The PFD takes inputs from the R counter and N counter and

produces an output proportional to the phase and frequency

difference between them. Figure 5 is a simpliﬁed schematic.

The functional block diagram for the ADF4217L family is shown

on page 1. The main blocks include a 22-bit input shift register,

a 14-bit R counter, and an N counter. The N counter is comprised

of a 6-bit A counter and an 11-bit B counter for the ADF4217L

and the ADF4218L. The 18-bit N counter on the ADF4219L

is comprised of a 13-bit B counter and a 5-bit A counter. Data

is clocked into the 22-bit shift register on each rising edge of

CLK. The data is clocked in MSB first. Data is transferred from

the shift register to one of four latches on the rising edge of LE.

The destination latch is determined by the state of the two con-

trol bits (C2, C1) in the shift register. These are the two LSBs,

DB1 and DB0 as shown in the timing diagram of Figure 1. The

truth table for these bits is shown in Table I.

CHARGE

PUMP

CLR1

R DIVIDER

DELAY

ELEMENT

Table I. C2, C1 Truth Table

Control Bits

C2 C1

Data Latch

CLR2

D2 Q2

IF R Counter

IF AB Counter (and Prescaler Select)

RF R Counter

DOWN

N DIVIDER

CPGND

RF AB Counter (and Prescaler Select)

R DIVIDER

N DIVIDER

CP OUTPUT

Figure 5. PFD Simplified Schematic

–10–

REV. B

1...7 8 91011 12 13...24

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