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ADF4218LBRU-REEL7 PDF预览

ADF4218LBRU-REEL7

更新时间： 2024-02-25 10:31:01
品牌 Logo 应用领域
罗彻斯特 - ROCHESTER 光电二极管
页数 文件大小 规格书
25页 963K
描述
PLL FREQUENCY SYNTHESIZER, 3000 MHz, PDSO20, MO-153AC, TSSOP-20

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中文翻译

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ADF4218LBRU-REEL7 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Active零件包装代码：TSSOP
包装说明：TSSOP,针数：20
Reach Compliance Code：unknown风险等级：5.14
其他特性：ALSO REQUIRES A 3V TO 5.5V SUPPLY模拟集成电路 - 其他类型：PLL FREQUENCY SYNTHESIZER
JESD-30 代码：R-PDSO-G20JESD-609代码：e0
长度：6.5 mm湿度敏感等级：1
功能数量：1端子数量：20
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：240认证状态：COMMERCIAL
座面最大高度：1.2 mm最大供电电压 (Vsup)：3.3 V
最小供电电压 (Vsup)：2.6 V标称供电电压 (Vsup)：3 V
表面贴装：YES温度等级：INDUSTRIAL
端子面层：TIN LEAD端子形式：GULL WING
端子节距：0.65 mm端子位置：DUAL
处于峰值回流温度下的最长时间：30宽度：4.4 mm
Base Number Matches：1

ADF4218LBRU-REEL7 数据手册

 浏览型号ADF4218LBRU-REEL7的Datasheet PDF文件第19页浏览型号ADF4218LBRU-REEL7的Datasheet PDF文件第20页浏览型号ADF4218LBRU-REEL7的Datasheet PDF文件第21页浏览型号ADF4218LBRU-REEL7的Datasheet PDF文件第23页浏览型号ADF4218LBRU-REEL7的Datasheet PDF文件第24页浏览型号ADF4218LBRU-REEL7的Datasheet PDF文件第25页 
ADF4217L/ADF4218L/ADF4219L  
RF  
IF  
OUT  
OUT  
V
V
V
P
P
DD  
100pF  
100pF  
18⍀  
18⍀  
18⍀  
18⍀  
V 2  
V
2
V 1  
DD  
V 1  
P
100pF  
100pF  
P
DD  
3.3k⍀  
3.3k⍀  
18⍀  
18⍀  
V
V
CC  
CC  
CP  
CP  
IF  
RF  
VCO190-200T  
VCO190-1750T  
450pF  
2.4pF  
760pF  
690pF  
1.5k⍀  
4.7k⍀  
ADF4217L/  
ADF4218L/  
ADF4219L  
7.5nF  
24nF  
LOCK  
DETECT  
MUXOUT  
100pF  
100pF  
RF  
IN  
IF  
IN  
REF  
IN  
51⍀  
51⍀  
CLK  
DATA  
LE  
SPI COMPATIBLE SERIAL BUS  
10MHz  
TCXO  
DECOUPLING CAPACITORS (22␮F/10pF) ONV , V OF THE ADF4217L/ADF4218L/ADF4219L.  
DD  
P
THETCXO AND ONV  
OFTHE VCOs HAVE BEEN OMITTED FROMTHE DIAGRAMTO AID CLARITY.  
CC  
Figure 8. Local Oscillator Design for WCDMA System  
In this circuit, the reference input signal is applied to the circuit  
at REFIN by a 10 MHz TCXO (temperature controlled crystal  
oscillator).  
SCLK  
MOSI  
CLK  
DATA  
LE  
ADF4217L/  
ADF4218L/  
ADF4219L  
ADuC812  
INTERFACING  
I/O PORTS  
The ADF4217L/ADF4218L/ADF4219L family has a simple  
SPI® compatible serial interface for writing to the device. SCLK,  
SDATA, and LE control the data transfer. When LE (latch  
enable) goes high, the 22 bits that have been clocked into the  
input register on each rising edge of SCLK will get transferred  
to the appropriate latch. See Figure 1 for the timing diagram  
and Table I for the latch truth table.  
MUXOUT  
(LOCK DETECT)  
Figure 9. ADuC812 to ADF421xL Interface  
ADSP2181 Interface  
Figure 10 shows the interface between the ADF4217L family and  
the ADSP-21xx digital signal processor. As previously discussed,  
the ADF4217L family needs a 22-bit serial word for each latch  
write. The easiest way to accomplish this using the ADSP-21xx  
family is to use the autobuffered transmit mode of operation  
with alternate framing. This provides a means for transmitting  
an entire block of serial data before an interrupt is generated.  
Set up the word length for eight bits and use three memory loca-  
tions for each 22-bit word. To program each 22-bit latch, store  
the three 8-bit bytes, enable the Autobuffered Mode, and then  
write to the transmit register of the DSP. This last operation  
initiates the autobuffer transfer.  
The maximum allowable serial clock rate is 20 MHz. This means  
that the maximum update rate possible for the device is 909 kHz  
or one update every 1.1 µs. This is certainly more than adequate  
for systems that will have typical lock times in hundreds of  
microseconds.  
ADuC812 Interface  
Figure 9 shows the interface to the ADuC812 MicroConverter®.  
Since the ADuC812 is based on an 8051 core, this interface can  
be used with any 8051 based microcontroller. The MicroConverter  
is set up for SPI Master Mode with CPHA = 0. To initiate the  
operation, the I/O port driving LE is brought low. Each latch of  
the ADF421xL family needs a 22-bit word. This is accomplished  
by writing three 8-bit bytes from the MicroConverter to the  
device. When the third byte has been written, the LE input should  
be brought high to complete the transfer.  
SCLK  
DT  
CLK  
DATA  
LE  
TFS  
ADF4217L/  
ADF4218L/  
ADF4219L  
ADSP-21xx  
On first applying power to the ADF4217L family, it needs four  
writes (one each to the R counter latch and the AB counter latch  
for both RF1 and RF2 side) for the output to become active.  
MUXOUT  
(LOCK DETECT)  
I/O FLAG  
When operating in the mode described, the maximum SCLOCK  
rate of the ADuC812 is 4 MHz. This means that the maximum  
rate at which the output frequency can be changed will be about  
180 kHz.  
Figure 10. ADSP-21xx to ADF421xL Interface  
REV. C  
–21–  
1...19202122232425

中文翻译

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