ADF4217L/ADF4218L/ADF4219L
RF Program Modes
Tables IV and VII show how to set up the RF program modes.
program the new frequency and to initiate Fastlock. To come
out of Fastlock, the RF CP Gain Bit should be returned to “0”
and the extra damping resistor switched out.
RF Charge Pump Currents
P13 sets the RF charge pump current. With P13 set to “0,” ICP is
1.0 mA. With P13 set to “1,” ICP is 4.0 mA. See Table VII.
APPLICATIONS SECTION
Local Oscillator for GSM Handset Receiver
The diagram in Figure 7 shows the ADF4217L/ADF4218L/
ADF4219L being used in a classic superheterodyne receiver to
provide the required LOs (local oscillators). In this circuit, the
Programmable RF AB Counter
If control bits C2, C1 are 1, 1, the data in the input register is used
to program the RF AB counter. For the ADF4217L/ADF4218L,
the AB counter consists of a 6-bit swallow counter (A counter)
and 11-bit programmable counter (B counter). Table VIII shows
the input register data format for programming the RF AB counter
and the possible divide ratios. The ADF4219L N counter consists
of a 13-bit B counter and 5-bit A counter. Table IX shows the
input register data format for programming the ADF4219L.
reference input signal is applied to the circuit at fREF and is
IN
being generated by a 13 MHz temperature controlled crystal
oscillator. In order to have a channel spacing of 200 kHz (the GSM
standard), the reference input must be divided by 65, using the
on-chip reference counter.
The RF output frequency range is 1050 MHz to 1085 MHz.
Loop filter component values are chosen so that the loop band-
width is 20 kHz. The synthesizer is set up for a charge pump
current of 4.0 mA, and the VCO sensitivity is 15.6 MHz/V.
The IF output is fixed at 125 MHz. The IF loop bandwidth is
chosen to be 20 kHz with a channel spacing of 200 kHz. Loop
filter component values are chosen accordingly.
RF Prescaler Value
P14 in the RF AB counter latch sets the RF prescaler value. For
the ADF4217L and ADF4218L family, 32/33 or 64/65 prescalers
are available. See Table VIII. For the ADF4219L, the prescaler
may be 16/17 or 32/33. See Table IX.
RF Power-Down
Tables VII, VIII, and IX show the power-down bits (Charge
Pump Bit used for asynchronous in the ADF4217L family). See
the Power-Down section for a functional description.
Local Oscillator for WCDMA Receiver
Figure 8 shows the ADF4217L/ADF4218L/ADF4219L being
used to generate the local oscillator frequencies in a wideband
CDMA (WCDMA) system.
RF Fastlock
The RF CP Gain Bit (P13) of the RF N Register in the ADF4217L
family is the Fastlock Enable Bit. The loop filter should be
designed for the lower current setting. When Fastlock is enabled,
the RF CP current is set to maximum value. Also, an extra loop
filter damping resistor to ground is switched in using the
MUXOUT pin, thus compensating for the change of loop
dynamics when in Fastlock Mode. Since the RF CP Gain Bit is
contained in the RF N counter, only one write is needed to
The RF output range needed is 1720 MHz to 1780 MHz. The
VCO190-1750T from Varil-L will accomplish that. Channel spacing
is 200 kHz, the loop bandwidth of the loop filter is 20 kHz, and the
VCO sensitivity is 32 MHz/V. A charge pump current of 4.0 mA
is used and the desired phase margin for the loop is 45 degrees.
The IF output is fixed at 200 MHz. The VCO190-200T is used.
It has a sensitivity of 11.5 MHz/V. Channel spacing and loop
bandwidth are chosen the same as the RF side.
RF
IF
OUT
OUT
V
V
V
P
P
DD
100pF
100pF
18⍀
18⍀
18⍀
V 2
V
2
V 1
DD
V 1
P
100pF
100pF
P
DD
3.3k⍀
3.3k⍀
18⍀
18⍀
V
V
CC
CC
CP
CP
RF
IF
VCO190-125T
VCO190-1068U
18⍀
620pF
400pF
620pF
620pF
9k⍀
5.8k⍀
ADF4217L/
ADF4218L/
ADF4219L
3.9nF
6nF
LOCK
DETECT
MUXOUT
100pF
100pF
RF
IN
IF
IN
V
DD
REF
51⍀
IN
51⍀
CLK
DATA
LE
SPI COMPATIBLE SERIAL BUS
10MHz
TCXO
DECOUPLING CAPACITORS (22F/10pF) ONV , V OF THE ADF4217L/ADF4218L/ADF4219L.
DD
P
THE TCXO AND ONV
OFTHE VCOs HAVE BEEN OMITTED FROMTHE DIAGRAMTO AID CLARITY.
CC
Figure 7. Local Oscillator Design for GSM Receiver
–20–
REV. C
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