ADF4216BRU-REEL

更新时间： 2024-01-31 19:20:23

品牌	Logo	应用领域
亚德诺 - ADI		射频
页数	文件大小	规格书
20页	220K
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ADF4216BRU-REEL 数据手册

ADF4216/ADF4217/ADF4218

INTERFACING

ADSP-2181 Interface

The ADF4216/ADF4217/ADF4218 family has a simple SPI-

compatible serial interface for writing to the device. SCLK,

SDATA, and LE (Latch Enable) control the data transfer. When

LE goes high, the 22 bits that have been clocked into the input

appropriate latch. See Figure 1 for the Timing Diagram and

Table I for the Latch Truth Table.

Figure 10 shows the interface between the ADF421x family and

the ADSP-21xx Digital Signal Processor. As previously noted,

the ADF421x family needs a 22-bit serial word for each latch

write. The easiest way to accomplish this using the ADSP-21xx

family is to use the Autobuffered Transmit Mode of operation

with Alternate Framing. This provides a means for transmitting

an entire block of serial data before an interrupt is generated.

Set up the word length for eight bits and use three memory

locations for each 22-bit word. To program each 22-bit latch,

store the three 8-bit bytes, enable the Autobuffered mode and

then write to the transmit register of the DSP. This last opera-

tion initiates the autobuffer transfer.

The maximum allowable serial clock rate is 20 MHz. This

means that the maximum update rate possible for the device is

909 kHz or one update every 1.1 ms. This is certainly more than

adequate for systems that will have typical lock times in hun-

dreds of microseconds.

ADuC812 Interface

Figure 9 shows the interface between the ADF421x family and

the ADuC812 microconverter. Since the ADuC812 is based on

an 8051 core, this interface can be used with any 8051-based

microcontroller. The microconverter is set up for SPI Master

Mode with CPHA = 0. To initiate the operation, the I/O port

driving LE is brought low. Each latch of the ADF421x family

needs a 22-bit word. This is accomplished by writing three 8-bit

bytes from the microconverter to the device. When the third

byte has been written, the LE input should be brought high to

complete the transfer.

SCLK

SDATA

ADF4216/

ADF4217/

ADF4218

ADSP-21xx

TFS

MUXOUT

(LOCK DETECT)

I/O FLAG

Figure 10. ADSP-21xx to ADF421x Family Interface

On ﬁrst applying power to the ADF421x family, it requires four

writes (one each to the R counter latch and the AB counter latch

for both RF1 and RF2 side) for the output to become active.

When operating in the mode described, the maximum SCLOCK

rate of the ADuC812 is 4 MHz. This means that the maximum

rate at which the output frequency can be changed will be about

180 kHz.

SCLOCK

MOSI

SCLK

SDATA

ADF4216/

ADF4217/

ADF4218

ADuC812

I/O PORTS

MUXOUT

(LOCK DETECT)

Figure 9. ADuC812 to ADF421x Family Interface

–19–

REV. 0

1...16 17 181920

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与ADF4216BRU-REEL相关器件

型号	品牌	描述	获取价格	数据表
ADF4216BRU-REEL7	ADI	IC PLL FREQUENCY SYNTHESIZER, 1200 MHz, PDSO20, TSSOP-20, PLL or Frequency Synthesis Circu	获取价格
ADF4216BRUZ	ADI	IC PLL FREQUENCY SYNTHESIZER, 1200 MHz, PDSO20, TSSOP-20, PLL or Frequency Synthesis Circu	获取价格
ADF4216BRUZ-REEL	ADI	IC PLL FREQUENCY SYNTHESIZER, 1200 MHz, PDSO20, TSSOP-20, PLL or Frequency Synthesis Circu	获取价格
ADF4216BRUZ-RL	ADI	Dual, Integer-N 0.5 GHz / 1.2 GHz PLL	获取价格
ADF4216BRUZ-RL7	ADI	IC PLL FREQUENCY SYNTHESIZER, 1200 MHz, PDSO20, TSSOP-20, PLL or Frequency Synthesis Circu	获取价格
ADF4217	ADI	Dual RF PLL Frequency Synthesizers	获取价格

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