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ADF4212LBRU PDF预览

ADF4212LBRU

更新时间: 2024-01-18 10:58:56
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
20页 241K
描述
Dual Low Power PLL Frequency Synthesizer

ADF4212LBRU 技术参数

是否无铅: 含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:TSSOP
包装说明:TSSOP, TSSOP20,.25针数:20
Reach Compliance Code:compliantECCN代码:5A991.B
HTS代码:8542.39.00.01风险等级:5.12
模拟集成电路 - 其他类型:PLL FREQUENCY SYNTHESIZERJESD-30 代码:R-PDSO-G20
JESD-609代码:e3长度:6.5 mm
湿度敏感等级:1功能数量:1
端子数量:20最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP20,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):260电源:3 V
认证状态:Not Qualified座面最大高度:1.2 mm
子类别:PLL or Frequency Synthesis Circuits最大供电电流 (Isup):10 mA
最大供电电压 (Vsup):3.3 V最小供电电压 (Vsup):2.7 V
标称供电电压 (Vsup):3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn)端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:40宽度:4.4 mm
Base Number Matches:1

ADF4212LBRU 数据手册

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ADF4212L  
PIN FUNCTION DESCRIPTION  
Mnemonic  
Description  
CPRF  
RF Charge Pump Output. When enabled, this provides ICP to the external RF loop filter, which in turn drives the  
external RF VCO.  
DGNDRF  
RFIN  
AGNDRF  
Digital Ground Pin for the RF Digital Circuitry  
Input to the RF Prescaler. This small signal input is normally ac-coupled from the RF VCO.  
Ground Pin for the RF Analog Circuitry  
FLO  
REFIN  
Multiplexed Output of RF/IF Programmable or Reference Dividers, RF/IF Fastlock Mode. CMOS output.  
Reference Input. This is a CMOS input with a nominal threshold of VDD/2 and an equivalent input resistance of 100 k.  
See Figure 2. This input can be driven from a TTL or CMOS crystal oscillator, or it can be ac-coupled.  
Digital Ground Pin for the IF Digital, Interface, and Control Circuitry  
DGNDIF  
MUXOUT  
This multiplexer output allows either the IF/RF Lock Detect, the scaled RF, scaled IF, or the scaled Reference Frequency  
to be accessed externally.  
CLK  
DATA  
LE  
Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into  
the 24-bit shift register on the CLK rising edge. This input is a high impedance CMOS input.  
Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This input is a high  
impedance CMOS input.  
Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of the four  
latches, the latch being selected using the control bits.  
RSET  
Connecting a resistor between this pin and ground sets the maximum RF and IF charge pump output current. The  
nominal voltage potential at the RSET pin is 0.66 V. The relationship between ICP and RSET is  
13.5  
RSET  
ICP MAX  
=
so, with RSET = 2.7 k, ICP MAX = 5 mA for both the RF and IF Charge Pumps.  
AGNDIF  
IFIN  
CPIF  
Ground Pin for the IF Analog Circuitry  
Input to the IF Prescaler. This small signal input is normally ac-coupled from the IF VCO.  
Output from the IF Charge Pump. This is normally connected to a loop filter that drives the input to an external VCO.  
Power Supply for the IF Charge Pump. This should be greater than or equal to VDD2. In systems where VDD2 is 3 V,  
it can be set to 5.5 V and used to drive a VCO with a tuning range up to 5.5 V.  
VP2  
V
DD2  
Power Supply for the IF, Digital, and Interface Section. Decoupling capacitors to the ground plane should be placed  
as close as possible to this pin. VDD2 should have a value of between 2.6 V and 3.3 V. VDD2 must have the same  
potential as VDD1.  
V
DD1  
Power Supply for the RF Section. Decoupling capacitors to the ground plane should be placed as close as possible to  
this pin. VDD1 should have a value of between 2.6 V and 3.3 V. VDD1 must have the same potential as VDD2.  
Power Supply for the RF Charge Pump. This should be greater than or equal to VDD1. In systems where VDD1 is 3 V,  
it can be set to 5.5 V and used to drive a VCO with a tuning range up to 5.5 V.  
VP1  
REV. 0  
–5–  

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