Data Sheet
ADF4169
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
18 SDV
CPGND 1
DD
2
MUXOUT
LE
AGND
AGND 3
RF
17
16
15
14
ADF4169
TOP VIEW
(Not to Scale)
B
4
DATA
CLK
IN
RF A 5
IN
AV
6
13 CE
DD
NOTES
1. THE LFCSP HAS AN EXPOSED PAD
THAT MUST BE CONNECTED TO AGND.
Figure 5. Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
Mnemonic Description
1
2, 3
4
CPGND
AGND
RFINB
Charge Pump Ground. This pin is the ground return path for the charge pump.
Analog Ground.
Complementary Input to the RF Prescaler. Decouple this pin to the ground plane with a small bypass capacitor,
typically 100 pF.
5
RFINA
AVDD
Input to the RF Prescaler. This small signal input is normally ac-coupled from the VCO.
Positive Power Supplies for the RF Section. Place decoupling capacitors to the ground plane as close as possible
to these pins.
6, 7, 8
9
REFIN
Reference Input. This CMOS input has a nominal threshold of DVDD/2 and an equivalent input resistance of 100 kΩ.
It can be driven from a TTL or CMOS crystal oscillator, or it can be ac-coupled.
10
11
12
DGND
SDGND
TXDATA
Digital Ground.
Digital Σ-Δ Modulator Ground. This pin is the ground return path for the Σ-Δ modulator.
Transmit Data Pin. This pin provides the transmitted data in FSK or PSK mode and also controls some ramping
functionality.
13
14
15
16
CE
Chip Enable (1.9 V Logic). A logic low on this pin powers down the device and places the charge pump output
into three-state mode.
Serial Clock Input. This input is used to clock in the serial data to the registers. The data is latched into the input
shift register on the CLK rising edge. This input is a high impedance CMOS input.
Serial Data Input. The serial data is loaded most significant bit (MSB) first; the three least significant bits (LSBs)
are the control bits. This input is a high impedance CMOS input.
Load Enable Input. When LE is high, the data stored in the input shift register is loaded into one of the eight
latches; the latch is selected using the control bits. This input is a high impedance CMOS input.
CLK
DATA
LE
17
18
MUXOUT
SDVDD
Multiplexer Output. This pin allows various internal signals to be accessed externally.
Power Supply for the Digital Σ-Δ Modulator. Place decoupling capacitors to the ground plane as close as
possible to this pin.
19
DVDD
Positive Power Supply for the Digital Section. Place decoupling capacitors to the digital ground plane as close
as possible to this pin.
20, 21
22
SW1, SW2
VP
Fast Lock Switches.
Charge Pump Power Supply. The voltage on this pin must be greater than or equal to AVDD.
23
RSET
Reset. Connecting a resistor between this pin and ground sets the maximum charge pump output current. The
relationship between ICP and RSET is as follows:
ICP_MAX = 24.48/RSET
where:
ICP_MAX = 4.8 mA.
RSET = 5.1 kΩ.
24
25
CP
Charge Pump Output. When the charge pump is enabled, this output provides ICP to the external loop filter,
which, in turn, drives the external VCO.
Exposed Pad. The LFCSP has an exposed pad that must be connected to AGND.
EPAD
Rev. 0 | Page 7 of 36
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