Datasheet > ADF41513_V01

ADF41513_V01

更新时间： 2022-02-26 11:45:59

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
30页	1391K
描述
26.5 GHz, Integer N/Fractional-N, PLL Synthesizer

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ADF41513_V01 数据手册

ADF41513

Data Sheet

Parameter

LOGIC INPUTS

Input Voltage

High (V_IH)

Min

Typ

Max

Unit

Test Conditions/Comments

1.4

The serial port interface (SPI) block can accept

both 1.8 V or 3.3 V logic inputs

Low (V_IL)

Input Current (I_INH, I_INL

Input Capacitance (C_IN)

LOGIC OUTPUTS

Output Voltage

High (V_OH)

0.6

µA

)

1.4

2.6

MUXOUT voltage = 1.8 V, DLD voltage = 1.8 V

MUXOUT voltage = 3.3 V, DLD voltage = 3.3 V

Low (V_OL)

0.4

Output High Current, Output Low

Current (I_OH, I_OL)

500

µA

POWER SUPPLIES

AV_DD1, AV_DD2, AV_DD3, AV_DD4, AV_DD5, V_P3.135

3.3

63.5

2.1

1.45

3.465

3.2

3.6

128.8

100

I_DD1

I_DD2

I_DD3

I_DD4

µA

Current drawn by AV_DD1

Current drawn by AV_DD2

Current drawn by AV_DD3

Current drawn by AV_DD4

Current drawn by AV_DD5

Current drawn by V_P

Total current drawn by AV_DDxand V_P

T_A= 25°C, CE is low, total of all rails

I_DD5

I_P

I_TOTAL

95.1

Power-Down Mode

NOISE CHARACTERISTICS

Normalized Phase Noise Floor

(PN_SYNTH

)

In Integer N Mode²

−235

dBc/Hz

PLL loop bandwidth (BW) = 1 MHz (Integer N

mode)

In Fractional-N Mode³

Normalized 1∕f Noise (PN_{1_f})³

SPURIOUS SIGNALS

−231

−128

dBc/Hz

PLL loop BW = 1 MHz (fractional-N mode)

10 kHz offset, normalized to 1 GHz

Reference Spurious

PFD Spurious

In-Band Integer Boundary

Spurious

−90

−87

−45

dBc

At reference = 100 MHz, PLL loop BW = 40 kHz

At PFD = 50 MHz, PLL loop BW = 40 kHz

10 kHz offset, PLL loop BW = 250 kHz

¹T_A= 25°C, AV_DDx= 3.3 V (where x = 1, 2, 3, or 4), prescaler (P) = 8/9, f_RFIN= 26.5 GHz, REF_IN= 124 MHz, PFD frequency input (f_PFD) = 124 MHz.

²The synthesizer phase noise floor is estimated by measuring the inband phase noise at the output of the VCO and subtracting 20 log N (where N is the N divider value)

and 10 log f_PFD. PN_SYNTHis the total phase noise measured at the VCO output (PN_TOT) − 10 log f_PFD− 20 log N.

³The PLL phase noise is composed of 1/f (flicker) noise plus the normalized PLL noise floor. The formula for calculating the 1/f noise contribution at an RF frequency, f_RF,

and at a frequency offset, f, is given by phase noise (PN) = P_{1_f}+ 10 log(10 kHz/f) + 20 log(f_RF/1 GHz). Both the normalized phase noise floor and flicker noise are

modeled in the ADIsimPLL.

Rev. 0 | Page 4 of 30

1 2 345 6 7...30

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