Datasheet > ADF41513BCPZ

ADF41513BCPZ

更新时间： 2024-02-12 17:50:57

品牌	Logo	应用领域
亚德诺 - ADI		信息通信管理
页数	文件大小	规格书
30页	1391K
描述
26.5 GHz, Integer N/Fractional-N, PLL Synthesizer

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ADF41513BCPZ 技术参数

是否无铅：	含铅	是否Rohs认证：	符合
生命周期：	Active	包装说明：	HVQCCN,
针数：	24	Reach Compliance Code：	compliant
风险等级：	5.66	模拟集成电路 - 其他类型：	PHASE LOCKED LOOP
JESD-30 代码：	S-XQCC-N24	长度：	4 mm
功能数量：	1	端子数量：	24
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	UNSPECIFIED	封装代码：	HVQCCN
封装形状：	SQUARE	封装形式：	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度（摄氏度）：	260	座面最大高度：	0.8 mm
最大供电电压 (Vsup)：	3.465 V	最小供电电压 (Vsup)：	3.135 V
标称供电电压 (Vsup)：	3.3 V	表面贴装：	YES
技术：	BICMOS	温度等级：	INDUSTRIAL
端子形式：	NO LEAD	端子节距：	0.5 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	40
宽度：	4 mm	Base Number Matches：	1

ADF41513BCPZ 数据手册

26.5 GHz, Integer N/Fractional-N,

PLL Synthesizer

Data Sheet

ADF41513

FEATURES

GENERAL DESCRIPTION

1 GHz to 26.5 GHz bandwidth

Ultralow noise PLL

Integer N = −235 dBc/Hz, fractional-N = −231 dBc/Hz

High maximum PFD frequency

The ADF41513 is an ultralow noise frequency synthesizer that

can be used to implement local oscillators (LOs) as high as

26.5 GHz in the upconversion and downconversion sections of

wireless receivers and transmitters.

Integer N = 250 MHz, fractional-N = 125 MHz

25-bit fixed/49-bit variable fractional modulus mode

Single-ended reference input

3.3 V power supply, 3.3 V charge pump

Integrated 1.8 V logic capability

Phase resync

Programmable charge pump currents: 16× range

Digital lock detect

The ADF41513 is designed on a high performance silicon

geranium (SiGe), bipolar complementary metal-oxide

semiconductor (BiCMOS) process, achieving a normalized

phase noise floor of −235 dBc/Hz. The phase frequency

detector (PFD) operates up to 250 MHz (integer N mode)/

125 MHz (fractional-N mode) for improved phase noise and

spur performance. The variable modulus, ∑-Δ modulator allows

extremely fine resolution when using a 49-bit divide value. The

ADF41513 can be used as an integer N phase-locked loop

(PLL), or it can be used as a fractional-N PLL with either a fixed

modulus for subhertz frequency resolution or variable modulus

for subhertz exact frequency resolution.

3-wire serial interface with register readback option

Hardware and software power-down mode

Operating range from −40°C to +105°C

APPLICATIONS

Test equipment and instrumentation

Wireless infrastructure

Microwave point to point and multipoint radios

Very small aperture terminal (VSAT) radios

Aerospace and defense

A complete PLL is implemented when the synthesizer is used

with an external loop filter and voltage controlled oscillator

(VCO). The 26.5 GHz bandwidth eliminates the need for a

frequency doubler or divider stage, simplifying system

architecture and reducing cost. The ADF41513 is packaged in a

compact, 24-lead, 4 mm × 4 mm LFCSP.

FUNCTIONAL BLOCK DIAGRAM

SET

DD1

DD2

DD3

DD4

DD5

ADF41513

REFERENCE

5-BIT

R COUNTER

×2

REF

DOUBLER

÷2

DIVIDER

PHASE

FREQUENCY

DETECTOR

–

CHARGE

PUMP

HIGH-Z

GND

DC1

DC2

LOCK

DETECT

OUTPUT

MUX

MUXOUT

–

N COUNTER

DLD

DIV

OUT

25-BIT FIXED/49-BIT VARIABLE

FRACTIONAL INTERPOLATOR

DATA

FRACTION

VALUE

INTEGER

VALUE

MODULUS

CLK

32-BIT

DATA

VALUE

DATA

REG1

REG2

1.8V

REGULATOR

GND

Figure 1.

Rev. 0

Document Feedback

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rightsof third parties that may result fromits use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks andregisteredtrademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Technical Support

www.analog.com

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