Data Sheet
ADF41513
PIN CONFIGURATION AND FUNCTION DESCRIPTION
1
2
3
18
17
16
15
14
13
GND
C
REG1
AV
MUXOUT
LE
DD1
DD1
AV
ADF41513
TOP VIEW
(Not to Scale)
DATA
CLK
RF B 4
IN
5
6
RF
AV
A
IN
CE
DD2
NOTES
1. EXPOSED PAD. THE EXPOSED PAD MUST
BE CONNECTED TO GND.
Figure 3. Pin Configuration
Table 5. Pin Function Descriptions
Pin No. Mnemonic Description
1
GND
Ground Pin.
2, 3
AVDD1
PFD and Up and Down Digital Driver Power Supply. Pin 2 and Pin 3 can be tied together. With Pin 2 and Pin 3 tied
together, place three parallel capacitors as close as possible to the AVDD1 pins: 10 µF, 100 nF, and 100 pF.
4
RFINB
Complementary Input to the RF Prescaler. In single-ended mode, decouple this pin to the ground plane with a
small bypass capacitor, typically 100 pF.
5
6
RFINA
AVDD2
Input to the RF Prescaler. AC-couple this signal to the external VCO.
RF Buffer and Prescaler Power Supply. Place three parallel capacitors as close as possible to the AVDD2 pin: 10 µF,
100 nF, and 100 pF.
7
AVDD3
AVDD4
AVDD5
REFIN
N Divider Power Supply. Place three parallel capacitors as close as possible to the AVDD3 pin: 10 µF, 100 nF, and
100 pF.
R Divider and Lock Detector Power Supply. Place three parallel capacitors as close as possible to the AVDD4 pin:
10 µF, 1 µF, and 100 nF. Pin 8 powers the internal low dropout (LDO) regulator for the reference divider.
Σ-Δ Modulator and SPI Power Supply. Place three parallel capacitors as close as possible to the AVDD5 pin: 10 µF,
1 µF, and 100 nF. This pin powers the internal LDO regulator for the Σ-Δ modulator.
Reference Input. The reference can accept either a single-ended CMOS (dc-coupled) or single-ended sine wave
(ac-coupled). The single-ended input has a nominal threshold of 1 V and a dc equivalent input resistance of 20 kΩ.
8
9
10
11
12
13
DLD
TXDATA
CE
Digital Lock Detect Pin. A logic high on this pin indicates PLL lock.
Transmit Data Pin. Pin 12 is not used. Connect Pin 12 to GND.
Chip Enable. A logic low on this pin powers down the device and puts the charge pump output into three-state
mode. Registers do not hold their values when CE is low. This pin only supports 3.3 V logic inputs.
14
15
16
17
18
19
CLK
Serial Clock Input. CLK clocks in the serial data to the registers. The data is latched into the 32-bit shift register on
the CLK rising edge. This input is a high impedance CMOS input.
Serial Data Input. The serial data is loaded most significant bit (MSB) first with the two least significant bits (LSBs) as
the control bits. This input is a high impedance CMOS input.
Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of the four
latches. Select the latch using the control bits.
Multiplexer Output. This multiplexer output allows the lock detect, the scaled RF, the scaled reference frequency,
logic high, logic low, or register readback data to be accessed externally.
Internal 1.8 V Regulator Output Pin. Place three parallel capacitors as close to the CREG1 pin as possible: 4.7 µF,
100 nF, and 1 nF.
Internal 1.8 V Regulator Output Pin. Place three parallel capacitors as close to the CREG2 pin as possible: 4.7 µF,
100 nF, and 1 nF.
DATA
LE
MUXOUT
CREG1
CREG2
20
21
22
23
DC1
DC2
VP
DC Bias Pin 1. Place a 1 µF capacitor in parallel with a 1 nF capacitor to ground, as close as possible to the DC1 pin.
DC Bias Pin 2. Place a 1 µF capacitor in parallel with a 1 nF capacitor to ground, as close as possible to the DC2 pin.
Charge Pump Power Supply.
Maximum Charge Pump Current Setting Resistor. Connecting a resistor between the RSET pin and GND sets the
maximum charge pump output current. The nominal voltage potential at the RSET pin is 0.66 V. The relationship
between ICP and RSET is ICP_MAX = 12.96/RSET. For example, with RSET = 2.7 kΩ, ICP MAX = 4.8 mA. The relationship between
bleed current (IBLEED) and RSET is IBLEED_MIN = 0.0103/RSET. For example, with RSET = 2.7 kΩ, IBLEED_MIN = 3.81 µA.
RSET
Rev. 0 | Page 7 of 30
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