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ADF4107BRU-REEL7 PDF预览

ADF4107BRU-REEL7

更新时间： 2024-01-23 02:49:15
品牌 Logo 应用领域
亚德诺 - ADI 光电二极管信息通信管理
页数 文件大小 规格书
20页 752K
描述
PLL Frequency Synthesizer

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ADF4107BRU-REEL7 技术参数

Source Url Status Check Date：2013-05-01 14:56:35.524是否无铅： 含铅
是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：TSSOP包装说明：MO-153AB, TSSOP-16
针数：16Reach Compliance Code：not_compliant
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：5.4Is Samacsys：N
模拟集成电路 - 其他类型：PLL FREQUENCY SYNTHESIZERJESD-30 代码：R-PDSO-G16
JESD-609代码：e0长度：5 mm
湿度敏感等级：1功能数量：1
端子数量：16最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装等效代码：TSSOP16,.25
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：240电源：3/3.3 V
认证状态：Not Qualified座面最大高度：1.2 mm
子类别：PLL or Frequency Synthesis Circuits最大供电电压 (Vsup)：3.3 V
最小供电电压 (Vsup)：2.7 V标称供电电压 (Vsup)：3 V
表面贴装：YES技术：BICMOS
温度等级：INDUSTRIAL端子面层：Tin/Lead (Sn85Pb15)
端子形式：GULL WING端子节距：0.65 mm
端子位置：DUAL处于峰值回流温度下的最长时间：20
宽度：4.4 mmBase Number Matches：1

ADF4107BRU-REEL7 数据手册

 浏览型号ADF4107BRU-REEL7的Datasheet PDF文件第3页浏览型号ADF4107BRU-REEL7的Datasheet PDF文件第4页浏览型号ADF4107BRU-REEL7的Datasheet PDF文件第5页浏览型号ADF4107BRU-REEL7的Datasheet PDF文件第7页浏览型号ADF4107BRU-REEL7的Datasheet PDF文件第8页浏览型号ADF4107BRU-REEL7的Datasheet PDF文件第9页 
ADF4107  
PIN CONFIGURATIONS AND FUNCTIONAL DESCRIPTIONS  
CSP  
TSSOP  
(Chip Scale Package)  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
V
R
P
SET  
CP  
DV  
DD  
MUXOUT  
LE  
CPGND  
AGND  
ADF4107  
TOP VIEW  
PIN 1  
15 MUXOUT  
14 LE  
CPGND 1  
AGND 2  
AGND 3  
INDICATOR  
RF  
B
DATA  
CLK  
IN  
(Not to Scale)  
13 DATA  
12 CLK  
11 CE  
ADF4107  
TOP VIEW  
RF  
A
IN  
RF B 4  
IN  
RF A 5  
IN  
CE  
AV  
DD  
DGND  
REF  
IN  
Figure 3. ADF4107 TSSOP (Top View)  
Figure 4. ADF4107 Chip Scale Package  
Table 4. Pin Functional Descriptions  
Mnemonic Function  
Connecting a resistor between this pin and CPGND sets the maximum charge pump output current. The nominal voltage  
potential at the RSET pin is 0.66 V. The relationship between ICP and RSET is  
25.5  
RSET  
RSET  
ICP MAX  
=
so, with RSET = 5.1 kΩ, ICP MAX = 5 mA.  
CP  
Charge Pump Output. When enabled, this pin provides ICP to the external loop filter, which in turn drives the external VCO.  
Charge Pump Ground. This is the ground return path for the charge pump.  
Analog Ground. This is the ground return path of the prescaler.  
CPGND  
AGND  
Complementary Input to the RF Prescaler. This point must be decoupled to the ground plane with a small bypass capacitor,  
typically 100 pF. See Figure 18.  
RFINB  
RFINA  
AVDD  
Input to the RF Prescaler. This small signal input is ac-coupled to the external VCO.  
Analog Power Supply. This voltage may range from 2.7 V to 3.3 V. Decoupling capacitors to the analog ground plane should  
be placed as close as possible to this pin. AVDD must be the same value as DVDD.  
Reference Input. This is a CMOS input with a nominal threshold of VDD/2 and a dc equivalent input resistance of 100 kΩ. See  
Figure 17. This input can be driven from a TTL or CMOS crystal oscillator or it can be ac-coupled.  
REFIN  
DGND  
CE  
Digital Ground.  
Chip Enable. A logic low on this pin powers down the device and puts the charge pump output into three-state mode. Taking  
the pin high will power up the device, depending on the status of the power-down bit, F2.  
Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into the 24-bit shift  
register on the CLK rising edge. This input is a high impedance CMOS input.  
CLK  
Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This input is a high impedance  
CMOS input.  
DATA  
LE  
Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of the four latches, the  
latch being selected using the control bits.  
This multiplexer output allows either the lock detect, the scaled RF, or the scaled reference frequency to be accessed  
externally.  
MUXOUT  
DVDD  
VP  
Digital Power Supply. This may range from 2.7 V to 3.3 V. Decoupling capacitors to the digital ground plane should be placed  
as close as possible to this pin. DVDD must be the same value as AVDD.  
Charge Pump Power Supply. This voltage should be greater than or equal to VDD. In systems where VDD is 3 V, it can be set to 5  
V and used to drive a VCO with a tuning range of up to 5 V.  
Rev. 0 | Page 6 of 20  
 
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