Datasheet > 信号电路 > 锁相环或频率合成电路> ADF4107BRU-REEL7

ADF4107BRU-REEL7

更新时间： 2024-02-02 03:57:18

品牌	Logo	应用领域
亚德诺 - ADI		光电二极管信息通信管理
页数	文件大小	规格书
20页	752K
描述
PLL Frequency Synthesizer

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技术参数
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ADF4107BRU-REEL7 技术参数

Source Url Status Check Date：	2013-05-01 14:56:35.524	是否无铅：	含铅
是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	TSSOP	包装说明：	MO-153AB, TSSOP-16
针数：	16	Reach Compliance Code：	not_compliant
ECCN代码：	EAR99	HTS代码：	8542.39.00.01
风险等级：	5.4	Is Samacsys：	N
模拟集成电路 - 其他类型：	PLL FREQUENCY SYNTHESIZER	JESD-30 代码：	R-PDSO-G16
JESD-609代码：	e0	长度：	5 mm
湿度敏感等级：	1	功能数量：	1
端子数量：	16	最高工作温度：	85 °C
最低工作温度：	-40 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	TSSOP	封装等效代码：	TSSOP16,.25
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：	240	电源：	3/3.3 V
认证状态：	Not Qualified	座面最大高度：	1.2 mm
子类别：	PLL or Frequency Synthesis Circuits	最大供电电压 (Vsup)：	3.3 V
最小供电电压 (Vsup)：	2.7 V	标称供电电压 (Vsup)：	3 V
表面贴装：	YES	技术：	BICMOS
温度等级：	INDUSTRIAL	端子面层：	Tin/Lead (Sn85Pb15)
端子形式：	GULL WING	端子节距：	0.65 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	20
宽度：	4.4 mm	Base Number Matches：	1

ADF4107BRU-REEL7 数据手册

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ADF4107

ADSP2181 Interface

Interfacing

Figure 29 shows the interface between the ADF4107 and the

ADSP21xx Digital Signal Processor. The ADF4107 needs a

24-bit serial word for each latch write. The easiest way to

accomplish this using the ADSP21xx family is to use the

autobuffered transmit mode of operation with alternate

framing. This provides a means for transmitting an entire block

of serial data before an interrupt is generated. Set up the word

length for 8 bits and use three memory locations for each 24-bit

word. To program each 24-bit latch, store the three 8-bit bytes,

enable the autobuffered mode, and then write to the transmit

transfer.

The ADF4107 has a simple SPI™ compatible serial interface for

writing to the device. CLK, DATA, and LE control the data

transfer. When LE (Latch Enable) goes high, the 24 bits that

have been clocked into the input register on each rising edge of

CLK will get transferred to the appropriate latch. See Figure 2

for the timing diagram and Table 5 for the Latch truth table.

The maximum allowable serial clock rate is 20 MHz. This

means that the maximum update rate possible for the device is

833 kHz or one update every 1.2 µs. This is certainly more than

adequate for systems that have typical lock times in hundreds of

microseconds.

ADuC812 Interface

SCLK

CLK

Figure 28 shows the interface between the ADF4107 and the

ADuC812 MicroConverter®. Since the ADuC812 is based on an

8051 core, this interface can be used with any 8051 based

microcontroller. The MicroConverter is set up for SPI master

mode with CPHA = 0. To initiate the operation, the I/O port

driving LE is brought low. Each latch of the ADF4107 needs a

24-bit word. This is accomplished by writing three 8-bit bytes

from the MicroConverter to the device. When the third byte has

been written, the LE input should be brought high to complete

the transfer.

DATA

TFS

ADSP21XX

ADF4107

I/O FLAGS

MUXOUT

(LOCK DETECT)

Figure 29. ADSP-21xx to ADF4107 Interface

PCB Design Guidelines for Chip Scale

Package

The lands on the chip scale package (CP-20) are rectangular.

The printed circuit board pad for these should be 0.1 mm

longer than the package land length and 0.05 mm wider than

the package land width. The land should be centered on the pad.

This will ensure that the solder joint size is maximized. The

bottom of the chip scale package has a central thermal pad.

On first applying power to the ADF4107, it needs four writes

(one each to the initialization latch, function latch, R counter

latch, and N counter latch) for the output to become active.

I/O port lines on the ADuC812 are also used to control power-

down (CE input) and to detect lock (MUXOUT configured as

lock detect and polled by the port input).

When operating in the mode described, the maximum

SCLOCK rate of the ADuC812 is 4 MHz. This means that the

maximum rate at which the output frequency can be changed

will be 166 kHz.

The thermal pad on the printed circuit board should be at least

as large as this exposed pad. On the printed circuit board, there

should be a clearance of at least 0.25 mm between the thermal

pad and the inner edges of the pad pattern. This will ensure that

shorting is avoided.

SCLOCK

MOSI

CLK

DATA

Thermal vias may be used on the printed circuit board thermal

pad to improve thermal performance of the package. If vias are

used, they should be incorporated in the thermal pad at 1.2 mm

pitch grid. The via diameter should be between 0.3 mm and

0.33 mm and the via barrel should be plated with 1 oz. copper

to plug the via.

ADuC812

ADF4107

I/O PORTS

MUXOUT

(LOCK DETECT)

The user should connect the printed circuit board thermal pad

to AGND.

Figure 28. ADuC812 to ADF4107 Interface

Rev. 0 | Page 19 of 20

1...16 17 181920

中文翻译

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ADF4107BRU-REEL7 替代型号

型号	品牌	替代类型	描述	数据表
ADF4107BRUZ-REEL7	ADI	类似代替	PLL Frequency Synthesizer
ADF4107BRUZ	ADI	完全替代	PLL Frequency Synthesizer
ADF4107BRU	ADI	完全替代	PLL Frequency Synthesizer

与ADF4107BRU-REEL7相关器件

型号	品牌	获取价格	描述	数据表
ADF4107BRUZ	ADI	获取价格	PLL Frequency Synthesizer
ADF4107BRUZ-REEL	ADI	获取价格	PLL Frequency Synthesizer
ADF4107BRUZ-REEL7	ADI	获取价格	PLL Frequency Synthesizer
ADF4108	ADI	获取价格	PLL Frequency Synthesizer
ADF4108BCPZ	ADI	获取价格	PLL Frequency Synthesizer
ADF4108BCPZ-RL	ADI	获取价格	PLL Frequency Synthesizer
ADF4108BCPZ-RL7	ADI	获取价格	PLL Frequency Synthesizer
ADF4108BRUZ	ADI	获取价格	PLL Frequency Synthesizer
ADF4108BRUZ-RL	ADI	获取价格	PLL Frequency Synthesizer
ADF4108BRUZ-RL7	ADI	获取价格	PLL Frequency Synthesizer

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