Datasheet > 信号电路 > 锁相环或频率合成电路> ADF4107BRU-REEL7

ADF4107BRU-REEL7

更新时间： 2024-01-31 19:42:32

品牌	Logo	应用领域
亚德诺 - ADI		光电二极管信息通信管理
页数	文件大小	规格书
20页	752K
描述
PLL Frequency Synthesizer

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技术参数
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ADF4107BRU-REEL7 技术参数

Source Url Status Check Date：	2013-05-01 14:56:35.524	是否无铅：	含铅
是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	TSSOP	包装说明：	MO-153AB, TSSOP-16
针数：	16	Reach Compliance Code：	not_compliant
ECCN代码：	EAR99	HTS代码：	8542.39.00.01
风险等级：	5.4	Is Samacsys：	N
模拟集成电路 - 其他类型：	PLL FREQUENCY SYNTHESIZER	JESD-30 代码：	R-PDSO-G16
JESD-609代码：	e0	长度：	5 mm
湿度敏感等级：	1	功能数量：	1
端子数量：	16	最高工作温度：	85 °C
最低工作温度：	-40 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	TSSOP	封装等效代码：	TSSOP16,.25
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：	240	电源：	3/3.3 V
认证状态：	Not Qualified	座面最大高度：	1.2 mm
子类别：	PLL or Frequency Synthesis Circuits	最大供电电压 (Vsup)：	3.3 V
最小供电电压 (Vsup)：	2.7 V	标称供电电压 (Vsup)：	3 V
表面贴装：	YES	技术：	BICMOS
温度等级：	INDUSTRIAL	端子面层：	Tin/Lead (Sn85Pb15)
端子形式：	GULL WING	端子节距：	0.65 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	20
宽度：	4.4 mm	Base Number Matches：	1

ADF4107BRU-REEL7 数据手册

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ADF4107

Initialization Latch Method

Apply V_DD

Program the initialization latch (11 in two LSBs of input word).

Make sure that the F1 bit is programmed to 0.

Note that there is an enable feature on the timer counter. It is

enabled when Fastlock Mode 2 is chosen by setting the fastlock

mode bit (DB10) in the function latch to 1.

Charge Pump Currents

Next, do a function latch load (10 in two LSBs of the control

word), making sure that the F1 bit is programmed to a 0.

Then do an R load (00 in two LSBs).

CPI3, CPI2, and CPI1 program Current Setting 1 for the charge

pump. CPI6, CPI5, and CPI4 program Current Setting 2 for the

charge pump. The truth table is given in Figure 25.

Then do an AB load (01 in two LSBs).

When the Initialization Latch is loaded, the following occurs:

Prescaler Value

1. The function latch contents are loaded.

P2 and P1 in the function latch set the prescaler values. The

prescaler value should be chosen so that the prescaler output

frequency is always less than or equal to 300 MHz. Thus, with

an RF frequency of 4 GHz, a prescaler value of 16/17 is valid but

a value of 8/9 is not valid.

2. An internal pulse resets the R, AB, and timeout counters to

load-state conditions and also three-states the charge

pump. Note that the prescaler band gap reference and the

oscillator input buffer are unaffected by the internal reset

pulse, allowing close phase alignment when counting

resumes.

3. Latching the first AB counter data after the initialization

word will activate the same internal reset pulse. Successive

AB loads will not trigger the internal reset pulse unless

there is another initialization.

PD Polarity

This bit sets the phase detector polarity bit. See Figure 25.

CP Three-State

CE Pin Method

This bit controls the CP output pin. With the bit set high, the CP

output is put into three-state. With the bit set low, the CP output

is enabled.

Apply V_DD

Bring CE low to put the device into power-down. This is an

asychronous power-down in that it happens immediately.

Program the function latch (10).

Program the R counter latch (00).

Program the AB counter latch (01).

Initialization Latch

The initialization latch is programmed when C2 and C1 are set

to 1 and 1. This is essentially the same as the function latch

(programmed when C2, C1 = 1, 0).

Bring CE high to take the device out of power-down. The R and

AB counters will now resume counting in close alignment.

Note that after CE goes high, a duration of 1 µs may be required

for the prescaler band gap voltage and oscillator input buffer

bias to reach steady state.

However, when the initialization latch is programmed an

additional internal reset pulse is applied to the R and AB

counters. This pulse ensures that the AB counter is at load point

when the AB counter data is latched and the device will begin

counting in close phase alignment.

CE can be used to power the device up and down in order to

check for channel activity. The input register does not need to

be reprogrammed each time the device is disabled and enabled

as long as it has been programmed at least once after V_DDwas

initially applied.

If the latch is programmed for synchronous power-down (CE

pin is high; PD1 bit is high; PD2 bit is low), the internal pulse

also triggers this power-down. The prescaler reference and the

oscillator input buffer are unaffected by the internal reset pulse

and so close phase alignment is maintained when counting

resumes.

Counter Reset Method

Apply V_DD

When the first AB counter data is latched after initialization, the

internal reset pulse is again activated. However, successive AB

counter loads after this will not trigger the internal reset pulse.

Do a Function Latch Load (10 in two LSBs). As part of this,

load 1 to the F1 bit. This enables the counter reset.

Do an R counter load (00 in two LSBs).

Do an AB counter load (01 in two LSBs).

Do a Function latch load (10 in two LSBs). As part of this,

load 0 to the F1 bit. This disables the counter reset.

Device Programming after Initial Power-Up

After initially powering up the device, there are three ways to

program the device.

This sequence provides the same close alignment as the

initialization method. It offers direct control over the internal

reset. Note that counter reset holds the counters at load point

and three-states the charge pump, but does not trigger

synchronous power-down.

Rev. 0 | Page 17 of 20

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中文翻译

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ADF4107BRU-REEL7 替代型号

型号	品牌	替代类型	描述	数据表
ADF4107BRUZ-REEL7	ADI	类似代替	PLL Frequency Synthesizer
ADF4107BRUZ	ADI	完全替代	PLL Frequency Synthesizer
ADF4107BRU	ADI	完全替代	PLL Frequency Synthesizer

与ADF4107BRU-REEL7相关器件

型号	品牌	获取价格	描述	数据表
ADF4107BRUZ	ADI	获取价格	PLL Frequency Synthesizer
ADF4107BRUZ-REEL	ADI	获取价格	PLL Frequency Synthesizer
ADF4107BRUZ-REEL7	ADI	获取价格	PLL Frequency Synthesizer
ADF4108	ADI	获取价格	PLL Frequency Synthesizer
ADF4108BCPZ	ADI	获取价格	PLL Frequency Synthesizer
ADF4108BCPZ-RL	ADI	获取价格	PLL Frequency Synthesizer
ADF4108BCPZ-RL7	ADI	获取价格	PLL Frequency Synthesizer
ADF4108BRUZ	ADI	获取价格	PLL Frequency Synthesizer
ADF4108BRUZ-RL	ADI	获取价格	PLL Frequency Synthesizer
ADF4108BRUZ-RL7	ADI	获取价格	PLL Frequency Synthesizer

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