ADF4002BCPZ-RL7

更新时间： 2024-02-20 11:53:20

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
24页	457K
描述
Phase Detector/Frequency Synthesizer

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数据手册

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ADF4002BCPZ-RL7 数据手册

ADF4002

TIMING CHARACTERISTICS

AV_DD= DV_DD= 3 V 10ꢀ, AV_DD≤ V_P≤ 5.5 V, AGND = DGND = CPGND = 0 V, R_SET= 5.1 kΩ, dBm referred to 50 Ω, T_A= T_MAXto T_MIN

unless otherwise noted.¹

Table 2.

Parameter

Limit (B Version)²

Unit

Test Conditions/Comments

DATA to CLK setup time

DATA to CLK hold time

CLK high duration

CLK low duration

CLK to LE setup time

LE pulse width

t₁

t₂

t₃

t₄

t₅

t₆

ns min

¹Guaranteed by design, but not production tested.

²Operating temperature range (B version) is –40°C to +85°C.

Timing Diagram

t₃

t₄

CLK

t₁

t₂

DB1 (CONTROL

BIT C2)

DB0 (LSB)

(CONTROL BIT C1)

DB2

DB23 (MSB)

DATA

DB22

t₆

t₅

Figure 2. Timing Diagram

Rev. 0 | Page 4 of 24

1 2 345 6 7...24

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