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ADCLK948BCPZ-REEL7 PDF预览

ADCLK948BCPZ-REEL7

更新时间: 2024-01-25 06:14:43
品牌 Logo 应用领域
亚德诺 - ADI 时钟驱动器逻辑集成电路PC
页数 文件大小 规格书
12页 366K
描述
Two Selectable Inputs, 8 LVPECL Outputs, SiGe Clock Fanout Buffer

ADCLK948BCPZ-REEL7 技术参数

是否无铅:含铅是否Rohs认证:符合
生命周期:Active零件包装代码:QFN
包装说明:HVQCCN, LCC32,.2SQ,20针数:32
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.42
Samacsys Confidence:Samacsys Status:Released
Samacsys PartID:579005Samacsys Pin Count:33
Samacsys Part Category:Integrated CircuitSamacsys Package Category:Other
Samacsys Footprint Name:QFN50P500X500X100-33NSamacsys Released Date:2017-01-11 11:21:59
Is Samacsys:N系列:948
输入调节:DIFFERENTIALJESD-30 代码:S-XQCC-N32
JESD-609代码:e3长度:5 mm
逻辑集成电路类型:LOW SKEW CLOCK DRIVER湿度敏感等级:3
功能数量:1反相输出次数:
端子数量:32实输出次数:8
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:UNSPECIFIED封装代码:HVQCCN
封装等效代码:LCC32,.2SQ,20封装形状:SQUARE
封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度(摄氏度):260
传播延迟(tpd):0.245 ns认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.25 ns座面最大高度:1 mm
最大供电电压 (Vsup):3.63 V最小供电电压 (Vsup):2.97 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:BIPOLAR温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn)端子形式:NO LEAD
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:40宽度:5 mm
最小 fmax:4500 MHzBase Number Matches:1

ADCLK948BCPZ-REEL7 数据手册

 浏览型号ADCLK948BCPZ-REEL7的Datasheet PDF文件第2页浏览型号ADCLK948BCPZ-REEL7的Datasheet PDF文件第3页浏览型号ADCLK948BCPZ-REEL7的Datasheet PDF文件第4页浏览型号ADCLK948BCPZ-REEL7的Datasheet PDF文件第6页浏览型号ADCLK948BCPZ-REEL7的Datasheet PDF文件第7页浏览型号ADCLK948BCPZ-REEL7的Datasheet PDF文件第8页 
ADCLK948  
ABSOLUTE MAXIMUM RATINGS  
DETERMINING JUNCTION TEMPERATURE  
Table 5.  
To determine the junction temperature on the application  
printed circuit board (PCB), use the following equation:  
Parameter  
Rating  
Supply Voltage  
VCC − VEE  
Input Voltage  
CLK0, CLK1, CLK0, CLK1, IN_SEL  
6 V  
TJ = TCASE + (ΨJT × PD)  
where:  
VEE − 0.5 V to  
VCC + 0.5 V  
TJ is the junction temperature (°C).  
T
CASE is the case temperature (°C) measured by the customer at  
CLK0, CLK1, CLK0, CLK1 to VTx Pin (CML,  
LVPECL Termination)  
40 mA  
the top center of the package.  
ΨJT is from Table 6.  
PD is the power dissipation.  
CLK0, CLK1 to CLK0, CLK1  
1.8 V  
2 V  
Input Termination, VTx to CLK0, CLK1, CLK0,  
and CLK1  
Values of θJA are provided for package comparison and PCB  
design considerations. θJA can be used for a first-order approxi-  
mation of TJ by the equation  
Maximum Voltage on Output Pins  
Maximum Output Current  
Voltage Reference (VREFx)  
Operating Temperature Range  
Ambient  
VCC + 0.5 V  
35 mA  
VCC to VEE  
TJ = TA + (θJA × PD)  
−40°C to +85°C  
150°C  
−65°C to +150°C  
where TA is the ambient temperature (°C).  
Junction  
Storage Temperature Range  
Values of θJB are provided in Table 6 for package comparison  
and PCB design considerations.  
Stresses above those listed under Absolute Maximum Ratings  
may cause permanent damage to the device. This is a stress  
rating only; functional operation of the device at these or any  
other conditions above those indicated in the operational  
section of this specification is not implied. Exposure to absolute  
maximum rating conditions for extended periods may affect  
device reliability.  
ESD CAUTION  
THERMAL PERFORMANCE  
Table 6.  
Parameter  
Symbol  
Description  
Value1  
Unit  
Junction-to-Ambient Thermal Resistance  
θJA  
Still Air  
0 m/sec Air Flow  
Moving Air  
Per JEDEC JESD51-2  
Per JEDEC JESD51-6  
49.8  
°C/W  
θJMA  
1 m/sec Air Flow  
2.5 m/sec Air Flow  
43.5  
39.0  
°C/W  
°C/W  
Junction-to-Board Thermal Resistance  
Moving Air  
θJB  
Per JEDEC JESD51-8  
1 m/sec Air Flow  
Junction-to-Case Thermal Resistance  
Moving Air  
Die-to-Heatsink  
Junction-to-Top-of-Package Characterization Parameter  
Still Air  
30.ꢀ  
8.8  
°C/W  
°C/W  
°C/W  
θJC  
Per MIL-STD 883, Method 1012.1  
Per JEDEC JESD51-2  
ΨJT  
0 m/sec Air Flow  
0.ꢀ  
1 Results are from simulations. The PCB is a JEDEC multilayer type. Thermal performance for actual applications requires careful inspection of the conditions in the  
application to determine if they are similar to those assumed in these calculations.  
Rev. 0 | Page 5 of 12  
 
 
 

ADCLK948BCPZ-REEL7 替代型号

型号 品牌 替代类型 描述 数据表
ADCLK948BCPZ ADI

完全替代

Two Selectable Inputs, 8 LVPECL Outputs, SiGe Clock Fanout Buffer

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