ADCLK905/ADCLK907/ADCLK925
Data Sheet
D
D
1
2
3
4
12
11
Q1
Q1
ADCLK925
TOP VIEW
10 Q2
Q2
NC
NC
(Not to Scale)
9
NOTES
1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.
2. EXPOSED PAD. THE EXPOSED PAD IS NOT ELECTRICALLY CONNECTED TO ANY PART OF THE CIRCUIT.
IT CAN BE LEFT FLOATING FOR OPTIMAL ELECTRICAL ISOLATION BETWEEN THE PACKAGE HANDLE
AND THE SUBSTRATE OF THE DIE. IT CAN ALSO BE SOLDERED TO THE APPLICATION BOARD IF IMPROVED
THERMAL AND/OR MECHANICAL STABILITY IS DESIRED. EXPOSED METAL AT THE CORNERS OF THE PACKAGE
IS CONNECTED TO THIS EXPOSED PAD. ALLOW SUFFICIENT CLEARANCE TO VIAS AND OTHER COMPONENTS.
Figure 6. ADCLK925 Pin Configuration
Table 6. Pin Function Descriptions for 1:2 ADCLK925 Buffer
Pin No.
Mnemonic
Description
1
D
Noninverting Input.
2
D
Inverting Input.
3, 4, 5, 6
7, 14
8, 13
9
NC
VEE
VCC
Q2
Q2
Q1
Q1
VREF
VT
No Connect. No physical connection to the die.
Negative Supply Voltage.
Positive Supply Voltage.
Inverting Output 2.
10
Noninverting Output 2.
11
Inverting Output 1.
12
Noninverting Output 1.
15
Reference Voltage. Reference voltage for biasing ac-coupled inputs.
Center Tap. Center tap of 100 Ω input resistor.
16
EPAD
Exposed Pad. The exposed pad is not electrically connected to any part of the circuit. It can be left floating for
optimal electrical isolation between the package handle and the substrate of the die. It can also be soldered to
the application board if improved thermal and/or mechanical stability is desired. Exposed metal at the corners
of the package is connected to this exposed pad. Allow sufficient clearance to vias and other components.
Rev. B | Page 8 of 16