Datasheet > ADC3562IRSBT

ADC3562IRSBT

更新时间： 2023-06-19 15:17:54

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单通道、16 位、25MSPS、低噪声、超低功耗、低延迟 ADC \| RSB \| 40 \| -40 to 105

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ADC3562IRSBT 数据手册

ADC3563

SBAS990 – FEBRUARY 2021

www.ti.com

Table 5-1. Pin Descriptions (continued)

I/O

DESCRIPTION

NAME

NO.

27,38,39

Do not connect

DIGITAL INTERFACE

DA0P

DA0M

DA1P

DA1M

Positive differential serial LVDS output for lane 0, channel A

Negative differential serial LVDS output for lane 0, channel A

Positive differential serial LVDS output for lane 1, channel A

Negative differential serial LVDS output for lane 1, channel A

Positive differential serial LVDS output for lane 0, channel B.

Used only in dual band complex decimation. Default is powered down.

DB0P

DB0M

DB1P

DB1M

Negative differential serial LVDS output for lane 0, channel B.

Used only in dual band complex decimation. Default is powered down.

Positive differential serial LVDS output for lane 1, channel B.

Used only in dual band complex decimation. Default is powered down.

Negative differential serial LVDS output for lane 1, channel B.

Used only in dual band complex decimation. Default is powered down.

DCLKP

Positive differential serial LVDS bit clock output.

Negative differential serial LVDS bit clock output.

Positive differential serial LVDS frame clock output.

Negative differential serial LVDS frame clock output.

Positive differential serial LVDS bit clock input.

Negative differential serial LVDS bit clock input.

DCLKM

FCLKP

FCLKM

DCLKINP

DCLKINM

POWER SUPPLY

AVDD

5,15,36

Analog 1.8-V power supply

Ground, 0 V

11,14,37,40,

PowerPad

GND

IOGND

IOVDD

21,30

Ground, 0 V for digital interface

1.8-V power supply for digital interface

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