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ADC14V155

更新时间： 2024-11-29 02:53:35
品牌 Logo 应用领域
美国国家半导体 - NSC 转换器模数转换器
页数 文件大小 规格书
22页 425K
描述
14-Bit, 155 MSPS, 1.1 GHz Bandwidth A/D Converter with

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中文翻译

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ADC14V155 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
Reach Compliance Code：unknown风险等级：5.86
Is Samacsys：N转换器类型：A/D CONVERTER
JESD-30 代码：S-PQCC-N48最大线性误差 (EL)：0.03%
位数：14功能数量：1
端子数量：48最高工作温度：85 °C
最低工作温度：-40 °C输出位码：OFFSET BINARY, 2'S COMPLEMENT BINARY
封装主体材料：PLASTIC/EPOXY封装代码：QCCN
封装等效代码：LCC48,.27SQ,20封装形状：SQUARE
封装形式：CHIP CARRIER电源：1.8,3.3 V
认证状态：Not Qualified子类别：Analog to Digital Converters
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子形式：NO LEAD
端子节距：0.5 mm端子位置：QUAD
Base Number Matches：1

ADC14V155 数据手册

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April 2007  
ADC14V155  
14-Bit, 155 MSPS, 1.1 GHz Bandwidth A/D Converter with  
LVDS Outputs  
General Description  
Features  
The ADC14V155 is a high-performance CMOS analog-to-  
digital converter with LVDS outputs. It is capable of converting  
analog input signals into 14-Bit digital words at rates up to 155  
Mega Samples Per Second (MSPS). Data leaves the chip in  
a DDR (Dual Data rate) format; this allows both edges of the  
output clock to be utilized while achieving a smaller package  
size. This converter uses a differential, pipelined architecture  
with digital error correction and an on-chip sample-and-hold  
circuit to minimize power consumption and the external com-  
ponent count, while providing excellent dynamic perfor-  
mance. A unique sample-and-hold stage yields a full-power  
bandwidth of 1.1 GHz. The ADC14V155 operates from dual  
+3.3V and +1.8V power supplies and consumes 951 mW of  
power at 155 MSPS.  
1.1 GHz Full Power Bandwidth  
■
■
■
■
■
■
■
■
Internal sample-and-hold circuit  
Low power consumption  
Internal precision 1.0V reference  
Single-ended or Differential clock modes  
Clock Duty Cycle Stabilizer  
Dual +3.3V and +1.8V supply operation (+/- 10%)  
Power-down and Sleep modes  
Offset binary or 2's complement output data format  
■
■
LVDS outputs  
48-pin LLP package, (7x7x0.8mm, 0.5mm pin-pitch)  
■
The separate +1.8V supply for the digital output interface al-  
lows lower power operation with reduced noise. A power-  
down feature reduces the power consumption to 15 mW while  
still allowing fast wake-up time to full operation. In addition  
there is a sleep feature which consumes 50 mW of power and  
has a faster wake-up time.  
Key Specifications  
Resolution  
14 Bits  
■
■
■
■
■
■
■
Conversion Rate  
155 MSPS  
71.7 dBFS (typ)  
86.9 dBFS (typ)  
11.5 bits (typ)  
1.1 GHz (typ)  
951 mW (typ)  
SNR (fIN = 70 MHz)  
SFDR (fIN = 70 MHz)  
ENOB (fIN = 70 MHz)  
Full Power Bandwidth  
Power Consumption  
The differential inputs provide a full scale differential input  
swing equal to 2 times the reference voltage. A stable 1.0V  
internal voltage reference is provided, or the ADC14V155 can  
be operated with an external reference.  
Clock mode (differential versus single-ended) and output data  
format (offset binary versus 2's complement) are pin-se-  
lectable. A duty cycle stabilizer maintains performance over  
a wide range of input clock duty cycles.  
Applications  
High IF Sampling Receivers  
■
■
■
■
■
■
Wireless Base Station Receivers  
Power Amplifier Linearization  
It is available in a 48-lead LLP package and operates over the  
industrial temperature range of −40°C to +85°C.  
Multi-carrier, Multi-mode Receivers  
Test and Measurement Equipment  
Communications Instrumentation  
Radar Systems  
■
Block Diagram  
30005202  
© 2007 National Semiconductor Corporation  
300052  
www.national.com  
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