Datasheet > ADC12DC080

ADC12DC080

更新时间： 2024-11-25 04:48:51

品牌	Logo	应用领域
美国国家半导体 - NSC		转换器
页数	文件大小	规格书
14页	343K
描述
Dual 12-Bit, 80/105 MSPS A/D Converter with CMOS Outputs

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ADC12DC080 数据手册

ADVANCE INFORMATION

September 2007

ADC12DC080/ADC12DC105

Dual 12-Bit, 80/105 MSPS A/D Converter with CMOS

Outputs

General Description

NOTE: This is Advance Information for products current-

ly in development. ALL specifications are design targets

and are subject to change.

Features

1 GHz Full Power Bandwidth

■

Internal sample-and-hold circuit and precision reference

Low power consumption

The ADC12DC080 and ADC12DC105 are high-performance

CMOS analog-to-digital converters capable of converting two

analog input signals into 12-bit digital words at rates up to

80/105 Mega Samples Per Second (MSPS) respectively.

These converters use a differential, pipelined architecture

with digital error correction and an on-chip sample-and-hold

circuit to minimize power consumption and the external com-

ponent count, while providing excellent dynamic perfor-

mance. A unique sample-and-hold stage yields a full-power

bandwidth of 1 GHz. The ADC12DC080/105 may be operated

from a single +3.3V power supply. A power-down feature re-

duces the power consumption to very low levels while still

allowing fast wake-up time to full operation. The differential

inputs provide a 2V full scale differential input swing. A stable

1.2V internal voltage reference is provided, or the AD-

C12DC080/105 can be operated with an external 1.2V refer-

ence. Output data format (offset binary versus 2's comple-

ment) and duty cycle stabilizer are pin-selectable. The duty

cycle stabilizer maintains performance over a wide range of

clock duty cycles.

Clock Duty Cycle Stabilizer

Single +3.3V supply operation

Power-down mode

Offset binary or 2's complement output data format

60-pin LLP package, (9x9x0.8mm, 0.5mm pin-pitch)

Key Specifications

For ADC12DC105

Resolution

Conversion Rate

SNR (f_IN= 240 MHz)

SFDR (f_IN= 240 MHz)

Full Power Bandwidth

Power Consumption

■

12 Bits

105 MSPS

67 dBFS (typ)

83 dBFS (typ)

1 GHz (typ)

■

800 mW (typ)

Applications

High IF Sampling Receivers

■

The ADC12DC080/105 is available in a 60-lead LLP package

and operates over the industrial temperature range of −40°C

to +85°C.

Wireless Base Station Receivers

Test and Measurement Equipment

Communications Instrumentation

Portable Instrumentation

■

Connection Diagram

30015401

300154

www.national.com

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与ADC12DC080相关器件

型号	品牌	获取价格	描述	数据表
ADC12DC080CISQ	NSC	获取价格	Dual 12-Bit, 80/105 MSPS A/D Converter with CMOS Outputs
ADC12DC080CISQ/NOPB	TI	获取价格	Dual 12-Bit, 80 MSPS A/D Converter with CMOS Outputs 60-WQFN -45 to 85
ADC12DC105	TI	获取价格	ADC12DC105 Dual 12-Bit, 105 MSPS A/D Converter with CMOS Outputs
ADC12DC105_14	TI	获取价格	Dual 12-Bit, 105 MSPS A/D Converter with CMOS Outputs
ADC12DC105CISQ	NSC	获取价格	Dual 12-Bit, 80/105 MSPS A/D Converter with CMOS Outputs
ADC12DC105CISQ/NOPB	TI	获取价格	双通道、12 位、105MSPS、1.0GHz 输入带宽模数转换器 (ADC) \| NKA
ADC12DC105CISQE/NOPB	TI	获取价格	双通道、12 位、105MSPS、1.0GHz 输入带宽模数转换器 (ADC) \| NKA
ADC12DJ1600	TI	获取价格	ADC12xJ1600 Quad, Dual, or Single Channel 1.6-GSPS, 12-Bit, Analog-to-Digital Converter (A
ADC12DJ1600AAV	TI	获取价格	ADC12xJ1600 Quad, Dual, or Single Channel 1.6-GSPS, 12-Bit, Analog-to-Digital Converter (A
ADC12DJ1600AAVQ1	TI	获取价格	ADC12xJ1600-Q1 Quad/Dual/Single Channel, 1.6-GSPS, 12-bit, Analog-to-Digital Converter (AD

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