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ADC12451CMJ

更新时间： 2024-11-24 22:53:35
品牌 Logo 应用领域
美国国家半导体 - NSC 转换器测试
页数 文件大小 规格书
18页 312K
描述
Dynamically-Tested Self-Calibrating 12-Bit Plus Sign A/D Converter with Sample-and-Hold

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ADC12451CMJ 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
包装说明：DIP, DIP24,.6Reach Compliance Code：unknown
ECCN代码：3A001.A.2.CHTS代码：8542.39.00.01
风险等级：5.89最大模拟输入电压：5.05 V
最小模拟输入电压：-5.05 V最长转换时间：15.65 µs
转换器类型：ADC, SUCCESSIVE APPROXIMATIONJESD-30 代码：R-GDIP-T24
JESD-609代码：e0最大线性误差 (EL)：0.061%
标称负供电电压：-5 V模拟输入通道数量：1
位数：12功能数量：1
端子数量：24最高工作温度：125 °C
最低工作温度：-55 °C输出位码：2'S COMPLEMENT BINARY
输出格式：PARALLEL, 8 BITS封装主体材料：CERAMIC, GLASS-SEALED
封装代码：DIP封装等效代码：DIP24,.6
封装形状：RECTANGULAR封装形式：IN-LINE
峰值回流温度（摄氏度）：NOT SPECIFIED电源：+-5 V
认证状态：Not Qualified采样速率：14.458 MHz
采样并保持/跟踪并保持：SAMPLE座面最大高度：4.572 mm
子类别：Analog to Digital Converters最大压摆率：10 mA
标称供电电压：5 V表面贴装：NO
技术：CMOS温度等级：MILITARY
端子面层：Tin/Lead (Sn/Pb)端子形式：THROUGH-HOLE
端子节距：2.54 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：15.24 mm
Base Number Matches：1

ADC12451CMJ 数据手册

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December 1994  
ADC12451 Dynamically-Tested Self-Calibrating  
12-Bit Plus Sign A/D Converter with Sample-and-Hold  
Y
Telecommunications  
General Description  
The ADC12451 is a CMOS 12-bit plus sign successive ap-  
proximation analog-to-digital converter whose dynamic  
specifications (S/N, THD, etc.) are tested and guaranteed.  
On request, the ADC12451 goes through a self-calibration  
cycle that adjusts linearity, zero and full-scale errors. The  
ADC12451 also has the ability to go through an Auto-Zero  
cycle that corrects the zero error during every conversion.  
Y
High Resolution Process Control  
Y
Instrumentation  
Features  
Y
Self-calibration provides excellent temperature stability  
Y
Y
Y
Internal sample-and-hold  
8-bit mP/DSP interface  
a
Bipolar input range with a single 5V reference  
The analog input to the ADC12451 is tracked and held by  
the internal circuitry, so an external sample-and-hold is not  
required. The ADC12451 has a S/H control input which di-  
rectly controls the track-and-hold state of the A/D. A unipo-  
Key Specifications  
Y
Resolution  
12 bits plus sign  
7.7 ms (max)  
83 kHz (max)  
73.5 dB (min)  
a
lar analog input voltage range (0V to  
a
5V) or a bipolar  
g
Y
Conversion Time  
b
range ( 5V to 5V) can be accommodated with 5V sup-  
plies.  
Y
Sampling Rate  
Y
Bipolar Signal/Noise  
The 13-bit data result is available on the eight outputs of the  
ADC12451 in two bytes, high-byte first and sign extended.  
The digital inputs and outputs are compatible with TTL or  
CMOS logic levels.  
Y
b
Total Harmonic Distortion  
78.0 dB (max)  
100 ns  
Y
Aperture Time  
Y
Aperture Jitter  
100 ps  
rms  
Y
g
Zero Error  
2 LSB (max)  
Y
g
Positive Full-Scale Error  
@
g
1.5 LSB (max)  
Applications  
Y
Y
Power Consumption  
5V  
113 mW (max)  
Digital Signal Processing  
Y
Audio  
Simplified Block Diagram  
Connection Diagram  
Dual-In-Line Package  
TL/H/11025–2  
Top View  
Ordering Information  
Industrial  
Package  
s
s
b
(
40 C  
T
85 C)  
§
ADC12451CIJ  
§
A
J24A  
Military  
s
Package  
s
b
(
55 C  
§
T
125 C)  
§
A
TL/H/11025–1  
ADC12451CMJ,  
ADC12451CMJ/883  
J24A  
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.  
C
1995 National Semiconductor Corporation  
TL/H/11025  
RRD-B30M115/Printed in U. S. A.  
1234567...18

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