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ADC10664 PDF预览

ADC10664

更新时间: 2024-02-06 11:24:02
品牌 Logo 应用领域
美国国家半导体 - NSC 转换器复用器
页数 文件大小 规格书
14页 277K
描述
10-Bit 360 ns A/D Converter with Input Multiplexer and Sample/Hold

ADC10664 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:DIP, DIP28,.6Reach Compliance Code:unknown
ECCN代码:3A001.A.2.CHTS代码:8542.39.00.01
风险等级:5.82最大模拟输入电压:6.3 V
最小模拟输入电压:-0.3 V最长转换时间:0.47 µs
转换器类型:ADC, FLASH METHODJESD-30 代码:R-GDIP-T28
JESD-609代码:e0长度:36.83 mm
最大线性误差 (EL):0.1%模拟输入通道数量:4
位数:10功能数量:1
端子数量:28最高工作温度:125 °C
最低工作温度:-55 °C输出位码:OFFSET BINARY
输出格式:PARALLEL, WORD封装主体材料:CERAMIC, GLASS-SEALED
封装代码:DIP封装等效代码:DIP28,.6
封装形状:RECTANGULAR封装形式:IN-LINE
峰值回流温度(摄氏度):NOT SPECIFIED电源:5 V
认证状态:Not Qualified采样速率:1.5 MHz
采样并保持/跟踪并保持:SAMPLE座面最大高度:5.715 mm
子类别:Analog to Digital Converters最大压摆率:30 mA
标称供电电压:5 V表面贴装:NO
技术:CMOS温度等级:MILITARY
端子面层:Tin/Lead (Sn/Pb)端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:15.24 mm
Base Number Matches:1

ADC10664 数据手册

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Pin Descriptions  
DVCC  
AVCC  
,
These are the digital and analog positive sup-  
ply voltage inputs. They should always be con-  
nected to the same voltage source, but are  
brought out separately to allow for separate  
bypass capacitors. Each supply pin should be  
bypassed with a 0.1 µF ceramic capacitor in  
parallel with a 10 µF tantalum capacitor to  
ground.  
V
IN0, VIN1  
,
These are the analog input pins. The  
ADC10662 has two inputs (VIN0 and VIN1) and  
V
IN2, VIN3  
the ADC10664 has four inputs (VIN0, VIN1  
,
VIN2 and VIN3). The impedance of the source  
should be less than 500for best accuracy  
and conversion speed. For accurate conver-  
sions, no input pin (even one that is not se-  
lected) should be driven more than 50 mV  
above VCC or 50 mV below ground.  
INT  
S /H  
RD  
This is the active low interrupt output. INT  
goes low at the end of each conversion, and  
returns to a high state following the rising edge  
of RD .  
GND, AGND, These are the power supply ground pins. The  
DGND  
ADC10662 and ADC10664 have separate  
analog and digital ground pins (AGND and  
DGND) for separate bypassing of the analog  
and digital supplies. The ground pins should  
be connected to a stable, noise-free system  
ground. Both pins should be returned to the  
same potential.  
This is the Sample/Hold control input. When  
this pin is forced low (and CS is low), it causes  
the analog input signal to be sampled and ini-  
tiates a new conversion.  
This is the active low Read control input.  
When this RD and CS are low, any data  
present in the output registers will be placed  
on the data bus.  
DB0–DB9  
These are the TRI-STATE output pins.  
SPEED  
ADJ  
By connecting a resistor between this pin and  
ground, the conversion time can be reduced.  
The specifications listed in the table of Electri-  
cal Characteristics apply for a speed adjust re-  
sistor (RSA) equal to 14.0 k(Mode 1) or 8.26  
k(Mode 2). See the Typical Performance  
Curves and the table of Electrical Characteris-  
tics.  
CS  
This is the active low Chip Select control input.  
When low, this pin enables the RD and S /H  
pins.  
S0, S1  
These pins select the analog input that will be  
connected to the A/D during the conversion.  
The input is selected based on the state of S0  
and S1 when S /H makes its High-to-Low tran-  
sition (See the Timing Diagrams). The  
ADC10664 includes both S0 and S1. The  
ADC10662 includes just S0.  
VREF−  
VREF+  
,
These are the reference voltage inputs. They  
may be placed at any voltage between GND  
and VCC, but VREF+ must be greater than  
V
REF−. An input voltage equal to VREF− pro-  
duces an output code of 0, and an input volt-  
age equal to (VREF+ − 1 LSB) produces an out-  
put code of 1023.  
3
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