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ADC1061 PDF预览

ADC1061

更新时间: 2024-01-09 17:35:26
品牌 Logo 应用领域
美国国家半导体 - NSC 转换器
页数 文件大小 规格书
11页 323K
描述
10-Bit High-Speed レP-Compatible A/D Converter with Track/Hold Function

ADC1061 技术参数

生命周期:Obsolete包装说明:DIE,
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.8
最长转换时间:1.8 µs转换器类型:ADC, FLASH METHOD
JESD-30 代码:R-XUUC-N20最大线性误差 (EL):0.19%
模拟输入通道数量:1位数:10
功能数量:1端子数量:20
最高工作温度:85 °C最低工作温度:-40 °C
输出位码:BINARY输出格式:PARALLEL, WORD
封装主体材料:UNSPECIFIED封装代码:DIE
封装形状:RECTANGULAR封装形式:UNCASED CHIP
认证状态:Not Qualified采样并保持/跟踪并保持:TRACK
标称供电电压:5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子形式:NO LEAD端子位置:UPPER
Base Number Matches:1

ADC1061 数据手册

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Typical Performance Characteristics  
Zero (Offset) Error  
vs Reference Voltage  
Linearity Error vs  
Reference Voltage  
DS010559-9  
DS010559-10  
Mode 1 Conversion Time  
vs Temperature  
Mode 2 Conversion Time  
vs Temperature  
DS010559-11  
DS010559-12  
mate is then used to control the multiplexer that connects the  
MSB Ladder to the sixteen comparators on the right. Note  
that the comparators on the left needn’t be very accurate;  
they simply provide an estimate of the input voltage. Only the  
sixteen comparators on the right and the six on the left are  
necessary to perform the initial six-bit flash conversion, in-  
stead of the 64 comparators that would be required using  
conventional half-flash methods.  
Functional Description  
The ADC1061 digitizes an analog input signal to 10 bits ac-  
curacy by performing two lower-resolution “flash” conver-  
sions. The first flash conversion provides the six most signifi-  
cant bits (MSBs) of data, and the second flash conversion  
provides the four least significant bits (LSBs).  
Figure 3 is a simplified block diagram of the converter. Near  
the center of the diagram is a string of resistors. At the bot-  
tom of the string of resistors are 16 resistors, each of which  
has a value 1/1024th the resistance of the whole resistor  
string. These lower 16 resistors (the LSB Ladder) therefore  
have a voltage drop of 16/1024, or 1/64th of the total refer-  
ence voltage (VREF+ − VREF−) across them. The remainder  
of the resistor string is made up of eight groups of eight resis-  
tors connected in series. These comprise the MSB Ladder.  
Each section of the MSB Ladder has 1/8th of the total refer-  
ence voltage across it, and each of the MSB resistors has  
1/64th of the total reference voltage across it. Tap points  
across all of these resistors can be connected, in groups, to  
the sixteen comparators at the right of the diagram.  
To perform a conversion, the estimator compares the input  
voltage with the tap voltages on the seven resistors on the  
left. The estimator decoder then determines which MSB Lad-  
der tap points will be connected to the sixteen comparators  
on the right. For example, assume that the estimator deter-  
mines that VIN is between 11/16 and 13/16 of VREF. The es-  
timator decoder will instruct the comparator mux to connect  
the 16 comparators to the taps on the MSB Ladder between  
10/16 and 14/16 of VREF. The 16 comparators will then per-  
form the first flash conversion. Note that since the compara-  
tors are connected to Ladder voltages that extend beyond  
the range indicated by the estimator circuit, errors in the es-  
timator as large as 1/16 of the reference voltage (64 LSBs)  
will be corrected. This first flash conversion produces the six  
most significant bits of data.  
On the left side of the diagram is a string of seven resistors  
connected between VREF+ − VREF−. Six comparators com-  
pare the input voltage with the tap voltages on the resistor  
string to provide an estimate of the input voltage. This esti-  
www.national.com  
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