AC Electrical Characteristics
The following specifications apply for V+ +5V, tr tf 20 ns, VREF(+) 5V, and VREF(−) GND unless otherwise specified.
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Boldface limits apply for TA TJ TMIN to TMAX; all other limits TA TJ 25˚C.
Symbol
tCONV
tCRD
Parameter
Conditions
Mode 1
Typical
(Note 7)
1.2
Limit
(Note 8)
1.8
Units
(Limits)
µs (Max)
Conversion Time from Rising Edge
of S /H to Falling Edge of INT
Conversion Time for MODE 2
(RD Mode)
Mode 2
1.8
20
2.4
50
µs (Max)
ns (Max)
ns (Max)
=
Mode 1; CL 100 pF
tACC1
tACC2
tSH
Access Time (Delay from Falling
Edge of RD to Output Valid)
Access Time (Delay from Falling
Edge of RD to Output Valid)
Minimum Sample Time
=
Mode 2; CL 100 pF
tCRD + 50
(Figure 1); (Note 9)
250
50
ns (Max)
ns (Max)
=
=
t
1H, t0H
TRI-STATE Control (Delay from Rising
Edge of RD to High-Z State)
Delay from Rising Edge of RD
to Rising Edge of INT
RL 1k, CL 10 pF
20
10
tINTH
50
ns (Max)
=
tID
tP
Delay from INT to Output Valid
Delay from End of Conversion
to Next Conversion
CL 100 pF
20
10
50
20
ns (Max)
ns (Max)
SR
Slew Rate for Correct
2.5
V/µs
Track-and-Hold Operation
Analog Input Capacitance
Logic Output Capacitance
Logic Input Capacitance
CVIN
COUT
CIN
35
5
pF
pF
pF
5
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is func-
tional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed speci-
fications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions.
Note 2: All voltages are measured with respect to GND, unless otherwise specified.
−
+
<
>
V ) the absolute value of current at that pin should be limited
Note 3: When the input voltage (V ) at any pin exceeds the power supply rails (V
IN
V
or V
IN
IN
to 5 mA or less. The 20 mA package input current limits the number of pins that can safely exceed the power supplies with an input of 5 mA to four.
Note 4: The maximum power dissipation must be derated at elevated temperatures and is dictated by T , θ and the ambient temperature, T . The maximum
JMAX JA
A
=
allowable power dissipation at any temperature is P
(T
JMAX
− T )/θ or the number given in the Absolute Maximum Ratings, whichever is lower. For this device,
D
A
JA
=
T
150˚C, and the typical thermal resistance (θ ) when board mounted is 47˚C/W for the plastic (N) package, 85˚C/W for the ceramic (J) package, and 65˚C/W
JMAX
JA
for the small outline (WM) package.
Note 5: Human body model, 100 pF discharged through a 1.5 kΩ resistor.
Note 6: See AN-450 “Surface Mounting Methods and Their Effect on Product Reliability” or the section titled “Surface Mount” found in a current National Semicon-
ductor Linear Data Book for other methods of soldering surface mount devices.
Note 7: Typicals are at 25˚C and represent most likely parametric norm.
Note 8: Limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).
Note 9: Accuracy may degrade if t is shorter than the value specified.
SH
TRI-STATE Test Circuits and Waveforms
DS010559-4
DS010559-3
www.national.com
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