Datasheet > ADC1015S

ADC1015S

更新时间： 2024-01-02 10:31:36

品牌	Logo	应用领域
艾迪悌 - IDT		双倍数据速率
页数	文件大小	规格书
40页	382K
描述
Single 10-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps with input buffer; CMOS or LVDS DDR digital outputs

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

ADC1015S 数据手册

ADC1015S series

Single 10-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps

with input buffer; CMOS or LVDS DDR digital outputs

Rev. 03 — 2 July 2012

Product data sheet

1. General description

The ADC1015S is a single channel 10-bit Analog-to-Digital Converter (ADC) optimized for

high dynamic performances and low power consumption at sample rates up to 125 Msps.

Pipelined architecture and output error correction ensure the ADC1015S is accurate

enough to guarantee zero missing codes over the entire operating range. Supplied from a

single 3 V source, it can handle output logic levels from 1.8 V to 3.3 V in CMOS mode,

because of a separate digital output supply.

The ADC1015S supports the Low Voltage Differential Signalling (LVDS) Double Data

Rate (DDR) output standard. An integrated Serial Peripheral Interface (SPI) allows the

user to easily configure the ADC.

The device also includes a SPI programmable full-scale to allow flexible input voltage

range from 1 V to 2 V (peak-to-peak). With excellent dynamic performance from the

baseband to input frequencies of 170 MHz or more, the ADC1015S is ideal for use in

communications, imaging and medical applications - especially in high Intermediate

Frequency (IF) applications because of the integrated input buffer. The input buffer

ensures that the input impedance remains constant and low and the performance

consistent over a wide frequency range.

2. Features and benefits

 SNR, 61.7 dBFS / SFDR, 86 dBc

 Input bandwidth, 600 MHz

 Power dissipation, 635 mW at 80 Msps,

including analog input buffer

 Sample rate up to 125 Msps

 10-bit pipelined ADC core

 Clock input divided by 2 for less jitter

contribution

 Serial Peripheral Interface (SPI)

 Duty cycle stabilizer

 Integrated input buffer

 Fast OuT-of-Range (OTR) detection

 Offset binary, two’s complement, gray

code

 Flexible input voltage range:

1 V (p-p) to 2 V (p-p)

 CMOS or LVDS DDR digital outputs

 Power-down mode and Sleep mode

 HVQFN40 package

 Pin compatible with the ADC1415S

series, the ADC1215S series and the

ADC1115S125

12 3 4 5 6 7...40

中文翻译

下载PDF

与ADC1015S相关器件

型号	品牌	获取价格	描述	数据表
ADC1015S065HN/C1	NXP	获取价格	Single 10-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps Rev. 01 - 12 April 2010 Prelimin
ADC1015S065HN-C1	IDT	获取价格	Single 10-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps with input buffer; CMOS or LVDS
ADC1015S080HN/C1	NXP	获取价格	Single 10-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps Rev. 01 - 12 April 2010 Prelimin
ADC1015S080HN-C1	IDT	获取价格	Single 10-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps with input buffer; CMOS or LVDS
ADC1015S105HN/C1	NXP	获取价格	Single 10-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps Rev. 01 - 12 April 2010 Prelimin
ADC1015S105HN-C1	IDT	获取价格	Single 10-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps with input buffer; CMOS or LVDS
ADC1015S125HN/C1	NXP	获取价格	Single 10-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps Rev. 01 - 12 April 2010 Prelimin
ADC1015S125HN-C1	IDT	获取价格	Single 10-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps with input buffer; CMOS or LVDS
ADC-101B	FARADAY	获取价格	VIDEO FRONT-END MODULES
ADC101C021	TI	获取价格	ADC081C021/ADC081C027 I2C-Compatible, 8-Bit Analog-to-Digital Converter with Alert

与ADC1015S相关文章

MBRS340T3G手册解读：参数说明、产品特性及应用
2024-06-28

8
PMOS管背靠背连接：串联还是并联？
2024-06-28

7
高压电解电容的分类与选型策略
2024-06-28

8
数码管：基本概念、分类、技术发展及市场趋势
2024-06-27

14

产品中心

服务支持

精选活动

关于我们

帮助中心

ADC1015S

ADC1015S 数据手册

与ADC1015S相关器件

与ADC1015S相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

ADC1015S

ADC1015S 数据手册

与ADC1015S相关器件

与ADC1015S相关文章

您还可以找

您在本页遇到什么问题？