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ADC1010S080HN/C1 PDF预览

ADC1010S080HN/C1

更新时间: 2024-01-24 22:14:52
品牌 Logo 应用领域
恩智浦 - NXP 转换器模数转换器双倍数据速率
页数 文件大小 规格书
36页 273K
描述
Single 10-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps; CMOS or LVDS DDR digital outputs

ADC1010S080HN/C1 技术参数

生命周期:Transferred零件包装代码:QFN
包装说明:HVQCCN,针数:40
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.59
Is Samacsys:N最大模拟输入电压:2 V
最小模拟输入电压:1 V转换器类型:ADC, PROPRIETARY METHOD
JESD-30 代码:S-PQCC-N40长度:6 mm
模拟输入通道数量:1位数:10
功能数量:1端子数量:40
最高工作温度:85 °C最低工作温度:-40 °C
输出位码:OFFSET BINARY, 2'S COMPLEMENT BINARY, GRAY CODE输出格式:SERIAL, PARALLEL, WORD
封装主体材料:PLASTIC/EPOXY封装代码:HVQCCN
封装形状:SQUARE封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
认证状态:Not Qualified采样速率:80 MHz
座面最大高度:1 mm标称供电电压:3 V
表面贴装:YES温度等级:INDUSTRIAL
端子形式:NO LEAD端子节距:0.5 mm
端子位置:QUAD宽度:6 mm
Base Number Matches:1

ADC1010S080HN/C1 数据手册

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ADC1010S series  
Single 10-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps;  
CMOS or LVDS DDR digital outputs  
Rev. 01 — 9 April 2010  
Preliminary data sheet  
1. General description  
The ADC1010S is a single-channel 10-bit Analog-to-Digital Converter (ADC) optimized for  
high dynamic performances and low power consumption at sample rates up to 125 Msps.  
Pipelined architecture and output error correction ensure the ADC1010S is accurate  
enough to guarantee zero missing codes over the entire operating range. Supplied from a  
single 3 V source, it can handle output logic levels from 1.8 V to 3.3 V in CMOS mode,  
thanks to a separate digital output supply. It supports the LVDS (Low Voltage Differential  
Signalling) DDR (Double Data Rate) output standard. An integrated SPI (Serial Peripheral  
Interface) allows the user to easily configure the ADC. The device also includes a SPI  
programmable full-scale to allow flexible input voltage range from 1 V to 2 V  
(peak-to-peak). With excellent dynamic performance from the baseband to input  
frequencies of 170 MHz or more, the ADC1010S is ideal for use in communications,  
imaging and medical applications.  
2. Features and benefits  
„ SNR, 62 dBFS; SFDR, 86 dBc  
„ Input bandwidth, 600 MHz  
„ Sample rate up to 125 Msps  
„ 10-bit pipelined ADC core  
„ Power dissipation, 430 mW at 80 Msps  
„ Serial Peripheral Interface (SPI)  
„ Duty cycle stabilizer  
„ Clock input divider by 2 for less jitter  
contribution  
„ Single 3 V supply  
„ Fast OuT of Range (OTR) detection  
„ Flexible input voltage range: 1 V p-p to „ INL ±0.07 LSB, DNL ±0.04 LSB  
2 V p-p  
„ CMOS or LVDS DDR digital outputs  
„ Offset binary, two’s complement, gray  
code  
„ Pin compatible with the ADC1410S  
„ Power-down and Sleep modes  
series and the ADC1210S series  
„ HVQFN40 package  
3. Applications  
„ Wireless and wired broadband  
„ Portable instrumentation  
communications  
„ Spectral analysis  
„ Imaging systems  
„ Ultrasound equipment  
„ Software define radio  

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