Datasheet > ADC09QJ1300

ADC09QJ1300

更新时间： 2024-02-19 00:18:27

品牌	Logo	应用领域
德州仪器 - TI		/
页数	文件大小	规格书
155页	6861K
描述
ADC09xJ1300 Quad, Dual, Single Channel, 1.3-GSPS, 9-bit Analog-to-Digital Converter (ADC) with JESD204C Interface

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ADC09QJ1300 数据手册

ADC09QJ1300, ADC09DJ1300, ADC09SJ1300

SBASAF6 – OCTOBER 2021

ADC09xJ1300 Quad, Dual, Single Channel, 1.3-GSPS, 9-bit Analog-to-Digital

Converter (ADC) with JESD204C Interface

1 Features

2 Applications

•

ADC Core:

– Resolution: 9 Bit

– Maximum sampling rate: 1.3 GSPS

– Non-interleaved architecture

– Internal dither reduces high-order harmonics

Performance specifications (–1 dBFS):

– SNR (100 MHz): 53.5 dBFS

•

Light detection and ranging (LiDAR)

Handheld test equipment

Multi-channel oscilloscopes and digitizers

Wireless communications test equipment

Optical coherent tomography (OCT)

Satellite communications (SATCOM)

•

3 Description

– ENOB (100 MHz): 8.5 Bits

ADC09xJ1300 is a family of quad, dual and single

channel, 9-bit, 1.3 GSPS analog-to-digital converters

(ADC). Low power consumption, high sampling rate

and 9-bit resolution makes the ADC09xJ1300 ideally

suited for suited for a variety of multi-channel

communications and test systems.

– SFDR (100 MHz): 64 dBc

– Noise floor (–20 dBFS): –143 dBFS

Full-scale input voltage: 800 mV_PP-DIFF

Full-power input bandwidth: 6 GHz

JESD204C Serial data interface:

•

– Support for 2 to 8 (Quad/Dual channel) or 1 to 4

(Single channel) total SerDes lanes

– Maximum baud-rate: 17.16 Gbps

– 64B/66B and 8B/10B encoding modes

– Subclass-1 support for deterministic latency

– Compatible with JESD204B receivers

Optional internal sampling clock generation

– Internal PLL and VCO (7.2–8.2 GHz)

SYSREF Windowing eases synchronization

Four clock outputs simplify system clocking

– Reference clocks for FPGA or adjacent ADC

– Reference clock for SerDes transceivers

Timestamp input and output for pulsed systems

Power consumption (1 GSPS):

Full-power input bandwidth (-3 dB) of 6 GHz enables

direct RF sampling of of L-band and S-band.

Device Information

PART NUMBER

PACKAGE⁽¹⁾

BODY SIZE (NOM)

ADC09QJ1300

•

ADC09DJ1300

ADC09SJ1300

FCBGA (144) 10.0 mm × 10.0 mm

•

(1) For all available packages, see the package option

addendum at the end of the data sheet.

•

– Quad Channel: 450 mW / channel

– Dual channel: 625 mW / channel

– Single channel: 940 mW

•

Power supplies: 1.1 V, 1.9 V

Quad Channel Block Diagram

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

12 3 4 5 6 7...155

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与ADC09QJ1300相关器件

型号	品牌	获取价格	描述	数据表
ADC09QJ1300AAV	TI	获取价格	ADC09xJ1300 Quad, Dual, Single Channel, 1.3-GSPS, 9-bit Analog-to-Digital Converter (ADC)
ADC09QJ1300AAVQ1	TI	获取价格	ADC09xJ1300-Q1 Quad/Dual/Single Channel, 1.3-GSPS, 9-bit Analog-to-Digital Converter (ADC)
ADC09QJ1300AAVT	TI	获取价格	ADC09xJ1300 Quad, Dual, Single Channel, 1.3-GSPS, 9-bit Analog-to-Digital Converter (ADC)
ADC09QJ1300AAVTQ1	TI	获取价格	ADC09xJ1300-Q1 Quad/Dual/Single Channel, 1.3-GSPS, 9-bit Analog-to-Digital Converter (ADC)
ADC09QJ1300-Q1	TI	获取价格	ADC09xJ1300-Q1 Quad/Dual/Single Channel, 1.3-GSPS, 9-bit Analog-to-Digital Converter (ADC)
ADC09QJ1300-Q1_V01	TI	获取价格	ADC09QJ1300-Q1 Quad Channel, 1.3 -GSPS, 9-bit Analog-to-Digital Converter (ADC) with JESD2
ADC09QJ1300-Q1_V02	TI	获取价格	ADC09QJ1300-Q1 Quad Channel, 1.3 -GSPS, 9-bit Analog-to-Digital Converter (ADC) with JESD2
ADC09QJ1300-Q1_V03	TI	获取价格	ADC09xJ1300-Q1 Quad/Dual/Single Channel, 1.3-GSPS, 9-bit Analog-to-Digital Converter (ADC)
ADC09QJ1300-Q1_V04	TI	获取价格	ADC09xJ1300-Q1 Quad/Dual/Single Channel, 1.3-GSPS, 9-bit Analog-to-Digital Converter (ADC)
ADC09QJ800	TI	获取价格	ADC09xJ800 Quad, Dual, Single Channel, 800-MSPS, 9-bit, Analog-to-Digital Converter (ADC)

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