ADC-208A
8-Bit, 20MSPS CMOS Flash A/D (ADC-208 Compatible)
Table 1. ADC-208A Output Code
TECHNICAL NOTES
1. The Reference ladder is floating with respect to VDD and may be referenced anywhere
within the specified limits. AC modulation of the reference voltage may also be utilized;
contact DATEL for further information.
ANALOG INPUT
CODE
DATA
1234
DATA 5678 DECIMAL
HEX
2. Clock Pulse Width – To improve performance when input signals may exceed Nyquist
bandwidths, the clock duty cycle can be adjusted so that the low portion (sample mode) of
the clock pulse is 15nSec wide. Reducing the sampling time period minimizes the amount
the input voltage slews and prevents the comparators from saturating.
3. A full-scale input produces all "1" on the data outputs.
4. DATEL uses the conservative definitions when specifying Intergal Linearity (end-point) and
Differential Linearity (code transition). The specifications using the less conservative definition
have also been provided as a comparative specification for products specified this way.
5. The process that is used to fabricate the ADC-208A eliminates the latchup phenomena
that has plagued CMOS devices in the past. These converters do not require external
protection diodes.
6. For clock rates less than 100kHz, there may be some degradation in offset and dif-
ferential nonlinearity. Performance may be improved by increasing the clock duty cycle
(decreasing the time spent in the sample mode).
7. Connect the converter appropriately; a typical connection circuit is shown in Figure 2.
Then apply an appropriate clock input.The reference input should be held to 0.1% accu-
racy or better. Do not use the +5V power supply as a reference without precision regulation
and high-frequency decoupling capacitors.
0.00V
+0.02V
+1.28V
+2.54V
+2.56V
+2.58V
+3.84V
+5.10V
Zero 0000
+1 LSB
0000
0000
0100
0111
1000
1000
1100
1111
0000
0001
0000
1111
0000
0001
0000
1111
0
00
01
40
7F
80
81
C0
FF
1
+¼ FS
64
+½ FS-ILSB
+½ FS
127
128
129
192
255
+½ FS+ILSB
+¾ FS
+FS
Note: Values shown here are for a +5.12Vdc reference. Scale other refereces propor-
tionally. (+REF=+5.12V, –REF=GND, ¼, ½, and ¾ References FS=No Connection)
8. Zero Adjustment - Adjusting the voltage at –REFERENCE (pin 3) adjusts the offset or zero
of the device. Pin 3 can be tied to GROUND for operation without adjustments
9. Full Scale Adjustment - Adjusting the voltage at +REFERENCE (pin 9) adjusts the gain of
the device. Pin 9 can be tied directly to a +5V reference for operation without adjustment.
10.Integral Nonlinearity Adjustments - Provision is made for optional adjustment of Integral
Nonlinearity through access of the reference's ¼, ½, and ¾ full scale points. For example,
the REF. MIDPOINT (pin 6) can be tied to a precision voltage halfway between +REFERENCE
and –REFERENCE. Pins 6, 18 and 20 should be bypassed to GROUND through 0.1μF capaci-
tors for operation without INL adjustments
Figure 2. ADC-208A Typical Connection Diagram
DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1151 USA
•
Tel: (508) 339-3000
•
www.datel.com
•
e-mail: help@datel.com
06 Jul 2015 ADC-208A.B05 Page 3 of 4