ADAU1702JSTZ

更新时间： 2024-02-15 09:06:51

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
52页	1175K
描述
SigmaDSP 28-56-Bit Audio Processor with Two ADCs and Four DACs

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数据手册

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ADAU1702JSTZ 数据手册

ADAU1702

SPECIFICATIONS

AVDD = 3.3 V, DVDD = 1.8 V, PVDD = 3.3 V, IOVDD = 3.3 V, ambient temperature 25° C, master clock input 12.288 MHz, unless

otherwise noted .

ANALOG PERFORMANCE

Table 1.

Parameter

Min Typ

Max

Unit

Test Conditions/Comments

ADC INPUTS

Number of Channels

Resolution

Stereo input

Bits

Full-Scale Input

100 (283)

μA_rms(μA_p-p

)

2 V_rmsinput with 20 kΩ (18 kΩ external + 2 kΩ

internal) series resistor

Signal-to-Noise Ratio

A-Weighted

100

Dynamic Range

A-Weighted

Total Harmonic Distortion + Noise

Interchannel Gain Mismatch

Crosstalk

−60 dB with respect to full-scale analog input

−3 dB with respect to full-scale analog input

Analog channel-to-channel crosstalk

100

−83

−82

1.5

mdB

250

+11

DC Bias

Gain Error

−11

DAC OUTPUTS

Number of Channels

Resolution

Two stereo output channels

Bits

Full-Scale Analog Output

Signal-to-Noise Ratio

A-Weighted

0.9 (2.5)

V_rms(V_P-P)

104

Dynamic Range

A-Weighted

Total Harmonic Distortion + Noise

Crosstalk

Interchannel Gain Mismatch

Gain Error

−60 dB with respect to full-scale analog output

104

−90

−100

mdB

−1 dB with respect to full-scale analog output

Analog channel-to-channel crosstalk

250

+10

−10

DC Bias

1.5

VOLTAGE REFERENCE

Absolute Voltage (CM, FILTA, FILTD)

AUXILIARY ADC

Full-Scale Analog Input

INL

DNL

Offset

Input Impedance

3.0

0.5

1.0

LSB

kΩ

Rev. 0 | Page 3 of 52

1 234 5 6 7...52

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