Four ADC, Two DAC,
Low Power Codec with Audio DSPs
ADAU1787
Data Sheet
Digital DVDD at 0.9 V typical
FEATURES
Low power (11.027 mW for typical stereo noise cancelling
solution)
Programmable FastDSP audio processing engine
Up to 768 kHz sample rate
Biquad filters, limiters, volume controls, mixing
28-bit SigmaDSP audio processing core
Visually programmable using SigmaStudio
Up to 50 MIPS performance
Low latency, 24-bit ADCs and DACs
96 dB SNR (signal through PGA and ADC with A-weighted
filter)
105 dB combined SNR (signal through DAC and headphone
with A-weighted filter)
I2C and SPI control interfaces, self boot from I2C EEPROM
Flexible GPIO
42-ball, 0.35 mm pitch, 2.695 mm × 2.320 mm WLCSP
APPLICATIONS
Noise cancelling handsets, headsets, and headphones
Bluetooth ANC handsets, headsets, and headphones
Personal navigation devices
Digital still and video cameras
Musical instrument effect processors
Multimedia speaker systems
Serial port fSYNC frequency from 8 kHz to 192 kHz
5 μs group delay (fS = 768 kHz) analog in to analog out with
FastDSP bypass
Smartphones
4 single-ended analog inputs, configurable as microphone
or line inputs
8 digital microphone inputs
2 analog differential audio outputs, configurable as either
line output or headphone driver
PLL supporting any input clock rate from 30 kHz to 27 MHz
Full-duplex, 4-channel ASRCs
2, 16-channel serial audio ports supporting I2S, left justified,
or up to TDM16
8 interpolators and 8 decimators with flexible routing
Power supplies
GENERAL DESCRIPTION
The ADAU1787 is a codec with four inputs and two outputs
that incorporates two digital signal processors (DSPs). The path
from the analog input to the DSP core to the analog output is
optimized for low latency and is ideal for noise cancelling
headsets. With the addition of just a few passive components,
the ADAU1787 provides a complete headset solution.
Note that throughout this data sheet, multifunction pins, such
as BCLK_0/MP1, are referred to either by the entire pin name
or by a single function of the pin, for example, BCLK_0, when
only that function is relevant.
Analog AVDD at 1.8 V typical
Digital I/O IOVDD at 1.1 V to 1.98 V
Rev. 0
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