Data Sheet
ADAU1860/ADAU1860-1
Three ADCs, One DAC, Low Power Codec with Audio DSPs
FEATURES
APPLICATIONS
► Programmable FastDSP audio processing engine
► Up to 768 kHz sample rate
► Biquad filters, limiters, volume controls, mixing
► Tensilica HiFi 3z DSP core
► Quad MAC per cycle: 24 × 24-bit multiplier and 64-bit accu-
mulator
► Flexible power operation mode: 24.576 MHz, 49.152 MHz,
73.728 MHz, and 98.304 MHz
► Noise canceling handsets, headsets, and headphones
► Bluetooth active noise canceling (ANC) handsets, headsets, and
headphones
► Personal navigation devices
► Digital still and video cameras
► Musical instrument effect processors
► Multimedia speaker systems
► Smartphones
► 336 kB total memory
► JTAG debug and trace
GENERAL DESCRIPTION
► Low latency, 24-bit ADCs and DAC
► 106 dB SNR (signal through ADC with A-weighted filter)
► 110 dB combined SNR (signal through DAC and headphone
with A-weighted filter)
► Programmable double precision MAC engine for maximum 24-
stage equalizer
The ADAU1860/ADAU1860-1 are codecs with three inputs and
one output that incorporate two digital signal processors (DSPs).
The path from the analog input to the DSP core to the analog
output is optimized for low latency and is ideal for noise canceling
earphones. With the addition of just a few passive components, the
ADAU1860/ADAU1860-1 provide a complete earphone solution.
► Serial port sample rates from 8 kHz to 768 kHz
► 5 μs group delay (fS = 768 kHz) analog in to analog out with
FastDSP bypass (zero instructions)
► 3 differential or single-ended analog inputs, configurable as mi-
crophone or line inputs
All specifications, functions, and features described in this data
sheet are shared between the ADAU1860 and the ADAU1860-1.
The ADAU1860 is only available for ordering by customers located
in the People's Republic of China (PRC). The ADAU1860-1 is
available for ordering by customers located outside of PRC.
► 8 digital microphone inputs
► Analog differential audio output, configurable as either line output
or headphone drive
Analog Devices is in the process of updating documentation to
provide terminology and language that is culturally appropriate. This
is a process with a wide scope and will be phased in as quickly as
possible. Thank you for your patience.
► 2 PDM output channels
► PLL supporting any input clock rate from 30 kHz to 36 MHz
► 4 channel asynchronous sample rate converters (ASRCs)
► 2, 16-channel serial audio ports supporting I2S, left justified, right
justified, or up to TDM16 (TDM12 in Turbo mode)
► 8 interpolators and 8 decimators with flexible routing
► Power supplies
► Digital I/O IOVDD at 1.1 V to 1.98 V
► Digital DVDD at 0.85 V to 1.21 V
► Headphone HPVDD at 1.8 V typical
► Headphone HPVDD_L at 1.2 V to HPVDD
► Control/communication interfaces
► I2C, SPI, or UART control ports
► Master quad SPI (QSPI)
► UART communication port
► Self-boot from QSPI flash
► Flexible GPIO and IRQ
► 56-ball, 0.35 mm pitch, 2.980 mm × 2.679 mm WLCSP
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable "as is". However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to
change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
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