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ADAU1463WBCPZ300RL PDF预览

ADAU1463WBCPZ300RL

更新时间： 2024-02-14 17:31:16
品牌 Logo 应用领域
亚德诺 - ADI DVD商用集成电路
页数 文件大小 规格书
207页 6267K
描述
SigmaDSP Digital Audio Processor

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ADAU1463WBCPZ300RL 技术参数

是否无铅： 含铅是否Rohs认证： 符合
生命周期：Active包装说明：HVQCCN,
针数：88Reach Compliance Code：compliant
风险等级：2.16Samacsys Description：Audio DSPs 32bit SigmaDSP Audio 16K/48K
其他特性：DVDD SUPPLY OF 1.2V NOMINAL IS USED FOR DIGITAL CIRCUITRY商用集成电路类型：CONSUMER CIRCUIT
JESD-30 代码：S-XQCC-N88长度：12 mm
功能数量：1端子数量：88
最高工作温度：105 °C最低工作温度：-40 °C
封装主体材料：UNSPECIFIED封装代码：HVQCCN
封装形状：SQUARE封装形式：CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
座面最大高度：0.9 mm最大供电电压 (Vsup)：3.63 V
最小供电电压 (Vsup)：2.97 V表面贴装：YES
温度等级：INDUSTRIAL端子形式：NO LEAD
端子节距：0.5 mm端子位置：QUAD
宽度：12 mm

ADAU1463WBCPZ300RL 数据手册

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Data Sheet  
ADAU1463/ADAU1467  
APPLICATIONS INFORMATION  
BULK BYPASS CAPACITORS  
AVDD PVDD IOVDD DVDD  
PCB DESIGN CONSIDERATIONS  
3.3V  
A solid ground plane is necessary for maintaining signal  
integrity and minimizing EMI radiation. If the PCB has two  
ground planes, they can be stitched together using vias that are  
spread evenly throughout the PCB.  
+
+
+
+
10µF  
10µF  
10µF  
10µF  
Figure 85. Bulk Bypass Capacitor Schematic  
Power Supply Bypass Capacitors  
Component Placement  
Bypass each power supply pin to its nearest appropriate ground  
pin with a single 100 nF capacitor and, optionally, with an  
additional 10 nF capacitor in parallel. Make the connections to  
each side of the capacitor as short as possible, and keep the trace  
on a single layer with no vias. For maximum effectiveness, place  
the capacitor either equidistant from the power and ground pins  
or, when equidistant placement is not possible, slightly nearer to  
the power pin (see Figure 83). Establish the thermal connections  
to the planes on the far side of the capacitor.  
Place all 100 nF bypass capacitors, which are recommended  
for every analog, digital, and PLL power ground pair, as near as  
possible to theADAU1463/ADAU1467. Bypass each of the AVDD,  
DVDD, PVDD, and IOVDD supply signals on the PCB with an  
additional single bulk capacitor (10 µF to 47 µF).  
Keep all traces in the crystal resonator circuit (see Figure 14) as  
short as possible to minimize stray capacitance. Do not connect  
any long PCB traces to the crystal oscillator circuit components  
because such traces may affect crystal startup and operation.  
POWER GROUND  
Grounding  
Use a single ground plane in the application layout. Place all  
components in an analog signal path away from digital signals.  
CAPACITOR  
TO POWER  
Exposed Pad PCB Design  
The device package includes an exposed pad for improved heat  
dissipation. When designing a PCB for such a package, consider  
the following:  
•
Place a copper layer, equal in size to the exposed pad, on all  
layers of the PCB, from top to bottom. Connect the copper  
layers to a dedicated copper PCB layer (see Figure 86).  
TO GROUND  
Figure 83. Recommended Power Supply Bypass Capacitor Layout  
Typically, a single 100 nF capacitor for each power ground pin  
pair is sufficient. However, if there is excessive high frequency  
noise in the system, use an additional 10 nF capacitor in parallel  
(see Figure 84). Place the 10 nF capacitor between the devices  
and the 100 nF capacitor, and establish the thermal connections  
on the far side of the 100 nF capacitor.  
TOP  
GROUND  
POWER  
BOTTOM  
VIAS  
COPPER SQUARES  
Figure 86. Exposed Pad Layout Example—Side View  
VIA TO  
VIA TO  
GROUND PLANE  
•
Place vias such that all layers of copper are connected,  
allowing for efficient heat and energy conductivity. For an  
example, see Figure 87, which shows 49 vias arranged in  
a 7 × 7 grid in the pad area.  
POWER PLANE  
100nF  
10nF  
Figure 84. Layout for Multiple Power Supply Bypass Capacitors  
To provide a current reservoir in case of sudden current spikes,  
use a 10 µF capacitor for each named supply (DVDD, AVDD,  
PVDD, and IOVDD) as shown in Figure 85.  
Figure 87. Exposed Pad Layout Example—Top View  
For detailed information, see the AN-772 Application Note,  
A Design and Manufacturing Guide for the Lead Frame Chip  
Scale Package (LFCSP).  
Rev. A | Page 203 of 207  
 
 
 
 
 
 
 
 
 
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